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* x86: use asmlinkage macro for smm_handler_tAaron Durbin2013-05-081-2/+3
* x86: add TSC_CONSTANT_RATE optionAaron Durbin2013-05-071-0/+4
* x86: use boot state callbacks to disable rom cacheAaron Durbin2013-05-011-3/+0
* Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region"Nico Huber2013-04-121-2/+0
* siemens/sitemp_g1p1: Make ACPI report the right mmconf regionPatrick Georgi2013-04-101-0/+2
* mtrr: add rom caching comment about hyperthreadsAaron Durbin2013-04-051-1/+5
* AMD: Drop six copies of wrmsr_amd and rdmsr_amdKyösti Mälkki2013-04-045-12/+20
* intel/microcode.h: Fix typo in comment: micr*o*codePaul Menzel2013-04-031-1/+1
* boot: add disable_cache_rom() functionAaron Durbin2013-04-011-0/+3
* x86: add rom cache variable MTRR index to tablesAaron Durbin2013-03-291-0/+3
* x86: mtrr: add CONFIG_CACHE_ROM supportAaron Durbin2013-03-291-0/+16
* x86: add new mtrr implementationAaron Durbin2013-03-291-11/+23
* x86: unify amd and non-amd MTRR routinesAaron Durbin2013-03-221-0/+2
* x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer2013-03-221-2/+2
* x86: protect against abi assumptions from compilerAaron Durbin2013-03-211-1/+1
* intel microcode: split up microcode loading stagesAaron Durbin2013-03-191-0/+7
* Google Link: Add remaining code to support native graphicsRonald G. Minnich2013-03-151-0/+7
* haswell: reserve default SMRAM spaceAaron Durbin2013-03-151-0/+3
* x86: SMM Module SupportAaron Durbin2013-03-141-0/+80
* GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel2013-03-0112-12/+12
* smm: Update rev 0x30101 SMM revision save stateAaron Durbin2013-02-271-12/+25
* AMD Family12h: Fix warningsMartin Roth2013-02-181-1/+0
* Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi2013-02-111-0/+3
* speedstep: Deduplicate some MSR identifiersPatrick Georgi2013-02-091-0/+3
* Unify assembler function handlingStefan Reinauer2012-12-061-1/+1
* Unify use of bool config variablesStefan Reinauer2012-11-201-1/+1
* SMM: Avoid use of global variables in SMI handlerDuncan Laurie2012-11-141-0/+3
* Pass the CPU index as a parameter to startup.Ronald G. Minnich2012-11-131-2/+2
* Fix gcc-4.7 building problem.Han Shen2012-11-121-1/+1
* Overhaul speedstep codeNico Huber2012-11-051-0/+74
* Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber2012-11-012-24/+7
* buildsystem: Make CPU microcode updating more configurableAlexandru Gagniuc2012-09-051-1/+1
* AMD northbridge: copy TOP_MEM and TOP_MEM2 for distributionKyösti Mälkki2012-08-091-0/+5
* Synchronize rdtsc instructionsStefan Reinauer2012-08-091-3/+16
* Move cpus_ready_for_init() to AMD K8Kyösti Mälkki2012-08-071-6/+0
* Revert "Use broadcast SIPI to startup siblings"Sven Schnelle2012-07-312-8/+13
* SMM: rename tseg_fixup to tseg_relocate and exportDuncan Laurie2012-07-251-0/+3
* SMM: Fix state save map for sandybridge and TSEGDuncan Laurie2012-07-241-0/+95
* Add code to read Intel microcode from CBFSVadim Bendebury2012-07-241-1/+10
* Intel cpus: Extend cache to cover complete Flash DeviceKyösti Mälkki2012-07-041-0/+6
* AGESA F15 wrapper for Trinityzbao2012-07-031-2/+11
* Use broadcast SIPI to startup siblingsSven Schnelle2012-07-022-13/+8
* Intel CPUs: execute microcode update only once per coreKyösti Mälkki2012-07-021-0/+1
* cbtypes.h: Unify cbtypes.h used in AMD board's codeVikram Narayanan2012-05-241-0/+66
* Clean up #ifsPatrick Georgi2012-05-082-3/+3
* SMM: unify mainboard APM command handlersStefan Reinauer2012-04-271-1/+3
* cpu/cpu.h: add ROMCC guardsStefan Reinauer2012-04-271-2/+3
* Revamp Intel microcode update codeStefan Reinauer2012-04-261-0/+21
* Replace cache control magic numbers with symbolsPatrick Georgi2012-04-251-0/+6
* Fixes and Sandybridge support for lapic cpu initStefan Reinauer2012-04-061-0/+3
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