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* pci_mmio_cfg: Rename pcicfg to pci_map_busJianjun Wang2021-11-291-10/+16
| | | | | | | | | | | Rename pcicfg to pci_map_bus and add prototype for the platforms not supporting ECAM. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Id9517c5ec4fa6b7c7a34552bfdc6d509927f6730 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* Rename ECAM-specific MMCONF KconfigsShelley Chen2021-11-101-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* pci_mmio_cfg: Always use pci_s_* functionsNico Huber2021-11-091-47/+12
| | | | | | | | | | | | | | When MMIO functions are available, the pci_s_* functions do exactly the same thing. Drop the redundant pci_mmio_* versions. Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* pci_mmio_cfg: Gather everything MMCONF (ECAM) relatedNico Huber2021-11-091-16/+16
| | | | | | | | | | | | | | | To ease code sharing with other MMIO-based configuration mechanisms, move everything MMCONF (more specifically ECAM) related to one spot and guard it. Change-Id: Idda2320c331499dabbee7447f1ad3e81340f2a25 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* pci_mmio_cfg: Move guard around pci_s_* functions to x86Nico Huber2021-11-091-2/+2
| | | | | | | | | | | | | | | | There is no platform in our tree that requires the PCI MMIO ops but doesn't want the pci_s_* definitions. The only case where we include the `pci_mmio_cfg.h` header but don't want the pci_s_* functions to use MMIO is on older x86 platforms, so move the guard there. Change-Id: Iaeed6ab43ad61b7c0e14572b12bf4ec06b6a26af Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* device/Kconfig: Introduce MMCONF_LENGTHAngel Pons2021-01-301-0/+4
| | | | | | | | | | | | This is necessary because ASL Memory32Fixed values cannot contain operations, even if they can be evaluated to constants. Add a sanity check in pci_mmio_cfg.h to ensure consistency with MMCONF_BUS_NUMBER. Change-Id: I8f0b5edf166580cc12c1363d8d6b6ef0f2854be9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50033 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/include: Drop unneeded empty linesElyes HAOUAS2020-09-141-1/+0
| | | | | | | | Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/include: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-13/+2
| | | | | | | | | | Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2fa3bad88bb5b068baa1cfc6bbcddaabb09da1c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Drop ROMCC code and header guardsArthur Heymans2019-12-191-3/+0
| | | | | | | | | Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* include/device: add a comment to pci mmio cfg addr helpers and cachingMichael Niewöhner2019-11-201-0/+6
| | | | | | | | | | | | Add a comment to the newly introduced MMIO address helpers for PCI config registers, that the pointer returned may change during the boot processs and, thus, must not be cached. Change-Id: Ieb90ae9d67a3b944d35587dec54756a17c27c86f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* include/device: add pci mmio cfg address helpersMichael Niewöhner2019-11-111-0/+18
| | | | | | | | | | Add helpers for getting the pci mmio cfg address for a register. Change-Id: Ie6fe22cacc7241a51d47cbe9fc64f30fa49d5a80 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36686 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* pci_mmio_cfg.h: Add a compile time error if MMCONF_BASE_ADDRESS is undefinedArthur Heymans2019-11-051-0/+4
| | | | | | | | | | | if CONFIG_MMCONF_SUPPORT is set, add a compiletime error if CONFIG_MMCONF_BASE_ADDRESS is not defined. Change-Id: I0439e994d170e8ec564ce188e82a850e2a286a66 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35883 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/pci: Rewrite PCI MMCONF with symbol referenceKyösti Mälkki2019-04-071-18/+37
| | | | | | | | | | | | | | | | | | | | The effect of pointer aliasing on writes is that any data on CPU registers that has been resolved from (non-const and non-volatile) memory objects has to be discarded and resolved. In other words, the compiler assumes that a pointer that does not have an absolute value at build-time, and is of type 'void *' or 'char *', may write over any memory object. Using a unique datatype for MMIO writes makes the pointer to _not_ qualify for pointer aliasing with any other objects in memory. This avoid constantly resolving the PCI MMCONF address, which is a derived value from a 'struct device *'. Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/pci_ops: Rename 'where' to 'reg'Kyösti Mälkki2019-03-131-24/+24
| | | | | | | | | | | One could understand 'where' as bus, device, function or register. Make it clear it is register. Change-Id: I95d0330ba40510e48be70ca1d8f58aca66c8f695 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* device/pci_ops: Unify signaturesKyösti Mälkki2019-03-131-12/+12
| | | | | | | | | | Use fixed width types and const pointers for dev. Change-Id: Ide3b70238479ad3e1869ed22aa4fa0f1ff8aa766 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
| | | | | | | | | | | | This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Remove DEFAULT_PCIEXBAR aliasKyösti Mälkki2019-03-061-7/+6
| | | | | | | | | | | | | The other DEFAULT_ entries are just immediate constants. Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* device/mmio.h: Add include file for MMIO opsKyösti Mälkki2019-03-041-1/+1
| | | | | | | | | | | MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/pci_ops: Avoid name collisionsKyösti Mälkki2019-03-031-8/+11
| | | | | | | | | | | | | | | Having different signatures for the PCI config accessors prevents them from having the same name in different stages. For now, work around this using __SIMPLE_DEVICE__. Change-Id: I20f56cfe3ac7dc4421e62a99ca91f39a857c0ccf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* device/pci_ops: Apply some symmetry in headersKyösti Mälkki2019-02-111-0/+42
| | | | | | | | | | | | | | | | To make PCI driver side arch-agnostic, function declarations have to be in symmetrical header file locations. From the driver side, the correct file to include is now <device/pci_ops.h> Change-Id: I8076a4867fd7472beaae0a021dcf0d9c7c905871 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* device/pci_ops: Move common pci_mmio_cfg.hKyösti Mälkki2019-02-111-0/+73
It is expected that method of accessing PCI configuration register space via memory-mapped region is arch-agnostic. Change-Id: Ide6baa00d611953aeb324be0d3561f464395c5eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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