coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	nb/intel/x4x: Remove apic 0 from devicetree	Arthur Heymans	2022-12-05	1	-6/+1
*	cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm	Arthur Heymans	2022-12-05	1	-3/+0
*	sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}	Elyes Haouas	2022-12-02	1	-1/+1
*	nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree	Arthur Heymans	2022-12-01	1	-2/+4
*	src/mainboard to src/security: Fix spelling errors	Martin Roth	2021-10-05	1	-1/+1
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	src/mainboard: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS	2020-05-10	1	-13/+1
*	mainboard/[a-f]*: Remove copyright notices	Patrick Georgi	2020-03-18	1	-1/+0
*	sb/intel/i82801gx: Add common LPC decode code	Arthur Heymans	2019-11-12	1	-0/+2
*	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans	2019-06-06	1	-1/+0
*	mb/*/devicetree.cb: Remove unavailable PCIe ports	Arthur Heymans	2019-06-05	1	-2/+0
*	mb//: Harmonise FD and devicetree on boards featuring ICH7	Arthur Heymans	2018-11-12	1	-3/+0
*	src/mainboard: Remove unneeded whitespace	Elyes HAOUAS	2018-10-18	1	-1/+1
*	mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree	Arthur Heymans	2018-09-15	1	-0/+4
*	mb/asrock/g41c-gs: Add g41m-gs variant	Arthur Heymans	2018-07-22	1	-0/+135