| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | {mb, soc}: Move mrc_cache invalidating logic into `memory` common code | Subrata Banik | 2022-03-15 | 1 | -6/+1 |
| * | {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype | Subrata Banik | 2022-03-15 | 1 | -2/+1 |
| * | mb, soc: Add the SPD_CACHE_ENABLE | Zhuohao Lee | 2022-03-02 | 1 | -1/+6 |
| * | mb, soc: change mainboard_memory_init_params prototype | Zhuohao Lee | 2022-02-25 | 1 | -1/+2 |
| * | mb/google/brya: Enable DDR4 SODIMM for brask | David Wu | 2021-10-04 | 1 | -0/+26 |
| * | mb/google/brya: Introduce new baseboard brask | Zhuohao Lee | 2021-08-03 | 1 | -20/+0 |
| * | soc/intel/alderlake: Update mainboard_memory_init_params() argument | Subrata Banik | 2021-06-24 | 1 | -2/+2 |
| * | Revert "mb/google/brya/brya0: Manually probe fw_config for DB_LTE" | Tim Wawrzynczak | 2021-05-24 | 1 | -2/+0 |
| * | mb/google/brya/brya0: Manually probe fw_config for DB_LTE | Tim Wawrzynczak | 2021-05-19 | 1 | -0/+2 |
| * | mb/google/brya: Add memory DQ map | Eric Lai | 2021-01-26 | 1 | -1/+12 |
| * | mb/google/brya: Add entry stubs of each stage | Eric Lai | 2020-12-02 | 1 | -0/+9 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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