index
:
coreboot.git
24.02_branch
4.1
4.10_branch
4.11_branch
4.12_branch
4.14_branch
4.15_branch
4.16_branch
4.18_branch
4.19_branch
4.2
4.20_branch
4.22_branch
4.3
4.4
4.8_branch
classic-2014.10
coreboot-v1
coreboot-v3
main
master
rampayload
Coreboot firmware sources
coreboot
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
mainboard
/
google
/
fizz
/
devicetree.cb
Commit message (
Expand
)
Author
Age
Files
Lines
*
mb/google/fizz: Enable Wake-on-Lan feature
Gaggery Tsai
2017-12-04
1
-0
/
+1
*
google/fizz: Disable unused i2c lines
Shelley Chen
2017-11-25
1
-21
/
+7
*
mb/google/fizz: Enable NIC leds
Gaggery Tsai
2017-11-09
1
-2
/
+8
*
mb/google/fizz: enable AER for PCIe root ports
Kane Chen
2017-10-16
1
-0
/
+16
*
mainboard/google/fizz: Enable Devslp for SATA port 1
Gaggery Tsai
2017-10-11
1
-1
/
+1
*
google/fizz: Enable wake-on-usb attach/detach
Shelley Chen
2017-10-02
1
-0
/
+26
*
mainboard/google/fizz: Enable support for DPTF
Tsai, Gaggery
2017-09-02
1
-0
/
+3
*
soc/intel/skylake: Add LPC and SPI lock down config option
Subrata Banik
2017-08-25
1
-0
/
+3
*
google/fizz: Override PL2 and SysPL2 values
Shelley Chen
2017-07-14
1
-1
/
+1
*
mainboard/google/fizz: Add audio devices
Kevin Cheng
2017-06-28
1
-0
/
+7
*
google/fizz: Enable cr50 over SPI
Shelley Chen
2017-06-20
1
-1
/
+15
*
google/fizz: Enable cr50 over i2c
Shelley Chen
2017-06-20
1
-1
/
+13
*
google/fizz: Enable devices under pci 1c.0
Shelley Chen
2017-05-05
1
-1
/
+1
*
google/fizz: Enable SATA on port 1
Shelley Chen
2017-04-27
1
-0
/
+1
*
mb/google/fizz: Configure PCI root port
Naresh G Solanki
2017-04-24
1
-12
/
+35
*
soc/intel/skylake: Split AC/DC settings for Deep Sx config
Duncan Laurie
2017-04-13
1
-2
/
+4
*
google/fizz: Update device tree from schematic
Shelley Chen
2017-03-23
1
-72
/
+34
*
google/fizz: Add new board
Shelley Chen
2017-03-23
1
-0
/
+279