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path: root/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/elkhartlake: Drop redundant PcieRpEnableNico Huber2024-01-171-3/+0
* mb/siemens/mc_ehl2: Set RGMII output impedance manuallyMario Scheithauer2023-03-021-0/+6
* mb/*: Remove lapic from devicetreeArthur Heymans2023-01-301-3/+1
* mb/siemens/mc_ehl2: Disable GSPI2 controllerMario Scheithauer2022-12-011-2/+0
* mb/siemens/mc_ehl2: Disable L1 prefetcherMario Scheithauer2022-11-251-0/+3
* mb/siemens/mc_ehl2: Enable downshift for Marvell PHYsMario Scheithauer2022-11-241-0/+3
* mb/siemens/mc_ehl2: Enable Marvell PHY interruptMario Scheithauer2022-11-241-0/+6
* mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driverMario Scheithauer2022-11-241-3/+39
* mb/siemens/mc_ehl2/devicetree.cb: Use RV3028 bus_speed instead of dummy i2c d...Jan Samek2022-11-181-6/+1
* mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDTWerner Zeh2022-11-091-0/+12
* mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OSWerner Zeh2022-11-091-1/+14
* mb/siemens/mc_ehl: Add FIVR config to devicetree for all variantsWerner Zeh2022-10-221-0/+6
* mb/siemens/mc_ehl2: Set I2C bus 1 speed to 100 kHzWerner Zeh2022-09-071-0/+3
* mb/siemens/mc_ehl2: Change to new RTC RV3028-C7Werner Zeh2022-09-071-9/+6
* mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edgeMario Scheithauer2022-05-211-0/+3
* mb/siemens/mc_ehl2: Quick fix for PSE TSN phy interface typeLean Sheng Tan2022-05-201-2/+0
* mainboard/**/devicetree.cb: Fix typoAngel Pons2022-05-171-1/+1
* soc/intel/elkhartlake: Enable SMBus depending on dev stateAngel Pons2022-05-171-1/+0
* mb/siemens/mc_ehl2: Set PCH TSN link speed to 1 Gbps in devicetreeMario Scheithauer2022-05-161-1/+1
* mb/siemens/mc_ehl2: Adjust PSE TSN settings in devicetreeMario Scheithauer2022-05-161-0/+4
* mb/siemens/mc_ehl: Disable HS400 mode for eMMCWerner Zeh2022-03-021-1/+1
* mb/siemens/mc_ehl2: Disable PCIe RPsMario Scheithauer2022-02-031-16/+4
* mb/siemens/mc_ehl2: Disable SATAMario Scheithauer2022-02-031-9/+1
* soc/intel/ehl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-211-3/+0
* mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetreeMario Scheithauer2021-11-151-2/+2
* mb/siemens/mc_ehl: Disable HECI #2 deviceMario Scheithauer2021-11-151-1/+0
* mb/siemens/mc_ehl2: Clean up devicetreeMario Scheithauer2021-11-041-64/+4
* mb/siemens/mc_ehl2: Configure SD card detect pin in devicetreeMario Scheithauer2021-11-041-0/+3
* mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetreeMario Scheithauer2021-11-041-8/+2
* mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetreeMario Scheithauer2021-11-041-13/+13
* mb/siemens/mc_ehl2: Adjust PCH serial IO settingsMario Scheithauer2021-10-141-17/+6
* mb/siemens/mc_ehl2: Adjust USB settingsMario Scheithauer2021-10-141-12/+12
* mb/siemens/mc_ehl2: Enable PCI devicesMario Scheithauer2021-10-141-4/+4
* mb/siemens/mc_ehl2: Disable SATA Port 0Mario Scheithauer2021-10-111-1/+1
* mb/siemens/mc_ehl2: Enable SD-CardMario Scheithauer2021-10-111-1/+1
* mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2Mario Scheithauer2021-10-111-17/+23
* mb/siemens/mc_ehl: Add a new variant mc_ehl2Werner Zeh2021-10-011-0/+262
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