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* src/mainboard/{siemens,starlabs}: Remove unused <console/console.h>Elyes HAOUAS2022-01-101-1/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I9116965512a5b3241fd7e28537d96637008b31e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb: Add space before closing comment block keywordPaul Menzel2021-12-231-1/+1
| | | | | | | | | | | | Run the command below to fix all occurrences. $ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,' Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/siemens/chili: Reuse options from Kconfig.nameFelix Singer2021-12-182-6/+2
| | | | | | | | | | Reuse the options from Kconfig.name for variant-specific selects. Change-Id: I35f51756180882d019a3ea8c555ccd18cd588f44 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/siemens/mc_ehl: Enable TPM in bootblockWerner Zeh2021-12-101-0/+1
| | | | | | | | | | | | Enable TPM init in bootblock so that all further stages and other CBFS files are directly measured into PCRs immediately instead of being logged into a buffer and replayed to the TPM in ramstage. Change-Id: Ib3ac29aa72abe8e967660ae7e8416aeb8812de26 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCIWerner Zeh2021-11-173-0/+28
| | | | | | | | | | | | | This board does not have a LPC or eSPI connection to the NC FPGA anymore and therefore IO port 0x80 is not useable for POST codes anymore. Enable the feature of sending the POST codes to the NC FPGA via PCI so that the POST codes are visbile again in coreboot. Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetreeMario Scheithauer2021-11-151-2/+2
| | | | | | | | | | | | With latest hardware revision all clock outputs will be used on this mainboard. For this reason set all clock source mappings to 'PCIE_CLK_FREE' to have a free running clock. Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl: Disable HECI #2 deviceMario Scheithauer2021-11-152-2/+0
| | | | | | | | | | | HECI #2 is not used for CSE communication. Therefore, it is not necessary to set the parameter 'Heci2Enable' in devicetree. Change-Id: I7012e4d877a464699727ca775af3f9965e0602e9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* treewide: Replace bad uses of `find_resource`Angel Pons2021-11-041-1/+1
| | | | | | | | | | | | | | | The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: I329efcb42a444b097794fde4f40acf5ececaea8c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
* mb/siemens/mc_ehl: Disable PMC low power modesWerner Zeh2021-11-041-0/+5
| | | | | | | | | | | | | All the mainboard variants of mc_ehl do not use the external switches for the bypass rails. Disable the matching UPDs and all the low power modes of the PMC. Change-Id: I08f4effe5c4d5845bed01dfe1bd1251c58012b7f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58895 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl: Disable all P-StatesWerner Zeh2021-11-041-0/+3
| | | | | | | | | | | | In order to get a reliable real-time performance disable all P-States for all mc_ehl based mainboard. Change-Id: I22857cc0f1476483ca82c1c872e4519e4b350ea9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/siemens/mc_ehl: Disable C-States for CPU and packageWerner Zeh2021-11-041-0/+10
| | | | | | | | | | | Disable all C-states other than C0/C1 for CPU and package. Change-Id: I2c163f859dab4b0dc02896c70122e993cdd3db72 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/siemens/mc_ehl2: Clean up devicetreeMario Scheithauer2021-11-041-64/+4
| | | | | | | | | | | | | | | | There are a bunch of devices in the devicetree that are disabled in FSP-S and not used on this board. Having them around in the devicetree, even if disabled, is not necessary and leads to a message in the log (left over static devices...check your devicetree). This commit cleans up devicetree.cb and removes all unused and disabled devices. Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58887 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl: Enable Row-Hammer preventionMario Scheithauer2021-11-041-0/+3
| | | | | | | | | | | As a prevention of Row-Hammer attacks enable the FSP-M parameter 'RhPrevention'. Change-Id: I52f68525e882aee26822d9b3c488639c00f27d17 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Configure SD card detect pin in devicetreeMario Scheithauer2021-11-041-0/+3
| | | | | | | | | | This configures GPIO GPP_G5 as an input pin for SD card detect. Change-Id: I708eb112fa054f2f88857001c409fb62493b6206 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetreeMario Scheithauer2021-11-041-8/+2
| | | | | | | | | | | | | | PCIe root ports #4 (00:1c.3) and #6 (00:1c.5) are currently not used on this mainboard and are not routed either, so remove them from the devicetree completely. PCIe root port #7 (00:1c.6) is connected and used. Add the missing settings for L1 substates and latency reporting to disable these features for this port as well. Change-Id: I47e8528bea993ed527a0aecdbc93b94bbd9a7a49 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetreeMario Scheithauer2021-11-041-13/+13
| | | | | | | | | | | | | | | | | | | On mc_ehl2 there are currently four of the six PCIe clocks used to drive PCIe devices. None of the used clock output is dedicated to a special device. Therefore do not use a port mapping of the clocks to avoid a stopping clock once a device is missing and the matching root port is disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free running clock. In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the value 0xFF to disable the CLKREQ-feature and unused clocks. Change-Id: I81419887b7f463a937917b971465245c1cb46b94 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
* mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetreeWerner Zeh2021-11-031-13/+13
| | | | | | | | | | | | | | | | | | | On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe devices. None of the used clock output is dedicated to a special device (CLK0 drives several devices on the mainboard, CLK1 and CLK2 are connected to a PCIe switch). Therefore do not use a port mapping of the clocks to avoid a stopping clock once a device is missing and the matching root port is disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free running clock. In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the value 0xFF to disable the CLKREQ-feature and unused clocks. Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58740 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetreeWerner Zeh2021-11-021-8/+2
| | | | | | | | | | | | | | PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this mainboard and are not routed either, so remove them from the devicetree completely. PCIe root port #7 (00:1c.6) is connected and used. Add the missing settings for L1 substates and latency reporting to disable these features for this port as well. Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58568 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl1: Clean up devicetreeWerner Zeh2021-11-021-74/+4
| | | | | | | | | | | | | | | | There are a bunch of devices in the devicetree that are disabled in FSP-S and not used on this board. Having them around in the devicetree, even if disabled, is not necessary and leads to a message in the log (left over static devices...check your devicetree). This commit cleans up devicetree.cb and removes all unused and disabled devices. Change-Id: Ia5ffb382e3524e61b8583aca801063942fe2f247 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/siemens/chili: Drop redundant Kconfig selectAngel Pons2021-10-271-1/+0
| | | | | | | | | | | The `SMBIOS_PROVIDED_BY_MOBO` Kconfig option is already selected through the `SECUNET_DMI` option. So, there's no need to select both of them. Change-Id: I784df87893043a011906af8808aff27d636c7626 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58625 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2: Adjust PCH serial IO settingsMario Scheithauer2021-10-141-17/+6
| | | | | | | | | | Correct the PCH serial IO settings, suitable for this mainboard. Change-Id: I3c9915b2d52fbc6a15ac1e68c77bfb3983f7b1cd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Adjust USB settingsMario Scheithauer2021-10-141-12/+12
| | | | | | | | | | Correct the USB settings, suitable for this mainboard. Change-Id: I691d91d2a76e27b8efdc18eeae737a78e9ae38fa Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Enable PCI devicesMario Scheithauer2021-10-141-4/+4
| | | | | | | | | | Correct the remaining PCI devices, differing from the ehl1 mainboard. Change-Id: I8112fa5ea86e879741061798530150701b759156 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Set coreboot ready LEDMario Scheithauer2021-10-141-0/+11
| | | | | | | | | | | This mainboard has its own coreboot ready LED. The LED is switched on via GPIO GPP_F20. Change-Id: I3570d691e90d2cb6e11b856b876f0327da118522 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl: Remove unneeded 'half_populated' variableWerner Zeh2021-10-121-4/+1
| | | | | | | | | | | | | | Since the DRAM population is fixed to both channels on all mc_ehl boards there is no need to have this 'half_populated' variable at all. Simply use a fixed 'false' in the call of 'memcfg_init()' and delete this variable here. Change-Id: I783c17e6d92322a8b0c094cce803108e718011fa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl: Use SPD data from HW-Info in the first placeWerner Zeh2021-10-121-3/+22
| | | | | | | | | | | | | | | | | | | The preferred location for the SPD data on mc_ehl based boards is the HW-Info data structure. Inside this structure there is a field of 128 bytes available for the SPD data. So in order to use it construct a buffer in memory which is 256 bytes long (as FSP requests minimum 256 bytes for the SPD data) and where the upper 128 bytes are taken from HW-Info holding the needed timing parameters for LPDDR4. If there is a case where HW-Info is not accessible or where the contained SPD data is not valid (by checking the CRC in HW-Info SPD) fall back to fixed SPD data set in CBFS. Change-Id: I2b6a1bde0306ba84f5214b876eaf76ca12d8f058 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer2021-10-112-0/+14
| | | | | | | | | | | | | | | | | | | | On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason, we have to adjust the PIR8 register (0x3150) which is responsible for PCIe device 25h. The bridge is connected to PCIe root port 7. The following routing is required: INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# TEST: - Boot into system software Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl: Add variant_mainboard_final()Mario Scheithauer2021-10-112-0/+11
| | | | | | | | | | | In upcoming patches, we need mainboard specific adjustments. Change-Id: Icf9d829b19b2d26a39ad34be4658064083e9da6d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl2: Enable LPC ComBMario Scheithauer2021-10-111-0/+1
| | | | | | | | | | | | | | Enable LPC ComB on this mainboard. TEST: - Boot Linux and check with 'dmesg | grep tty' Change-Id: I7ec58685a723c177df18144011934b206e6425d0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer2021-10-111-1/+0
| | | | | | | | | | | | This mainboard uses an eSPI-to-LPC bridge for console output. For this reason, the internal LPSS UART must be disabled. Change-Id: I86777cf719def331f4d257ddd94e9a87125ebce8 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl2: Adjust GPIOsMario Scheithauer2021-10-111-54/+35
| | | | | | | | | | | Set the GPIOs according to the circuit diagram for this mainboard. Change-Id: I19dc24a16ee9f533b45879bf60fb441e24018cc8 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl2: Disable SATA Port 0Mario Scheithauer2021-10-111-1/+1
| | | | | | | | | | | | This mainboard has only SATA Port 1 available with no device sleep feature. Change-Id: I338833f2f9bcb407599cfc676ead0b8a9d7379bd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl2: Enable SD-CardMario Scheithauer2021-10-111-1/+1
| | | | | | | | | | | This mainboard has SD slot available and therefore it should be enabled. Change-Id: I0c97e2dc589bf6b89713a473925e42a20278f457 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2Mario Scheithauer2021-10-111-17/+23
| | | | | | | | | | | | | | | | This board has the RTC RX6110SA connected to the I2C2 instead of SMBus as in mc_ehl1. Set the bus speed for I2C2 to 100 kHz, since this RTC only supports the standard speed. TEST: - Console Log shows no errors for RX6110SA during I2C2 init - Finalize device for I2C 00:32 shows correct date and time Change-Id: I679c6397fa0d213a25eebaf8a9e0bda9941acd26 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Update SPD for DDR4 devicesMario Scheithauer2021-10-111-3/+3
| | | | | | | | | | | | | | | | | | | | | | Since this variant uses different DDR4 devices compared to mc_ehl1 in a memory down configuration, the SPD data file must be adapted. In a first configuration we use Micron MT53D512M32D2NP modules. Following values were adjusted according to this board characteristic and with help of Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules JEDEC Spec and the Specification for this Micron modules itself: - SPD Byte 4 - only 4Gb density instead of 8Gb for mc_ehl1 - SPD Byte 5 - different Row and Column Address Bits - SPD Byte 29/30 - 4Gb LPDDR4 needs 130ns tRFCab - SPD Byte 31/32 - 4Gb LPDDR4 needs 60ns tRFCpb Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl: Move UART_FOR_CONSOLE switch to variant levelWerner Zeh2021-10-013-5/+8
| | | | | | | | | | | | There are currently two variants for mc_ehl where different UARTs are used for the console. Move the Kconfig switch UART_FOR_CONSOLE to the Kconfig of the variant and select the matching value there. Change-Id: I7152013a0e32ff151b92932a47953705e591dc0d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58052 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl: Add a new variant mc_ehl2Werner Zeh2021-10-0110-0/+605
| | | | | | | | | | | | Add a new variant of the mc_ehl board called mc_ehl2. This patch just copies the files and renames things where needed. Following patches will adapt the needed features for this new variant. Change-Id: I3ec3c091017fd66fe6a09216203cdc7c9e833846 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/siemens/mc_ehl1: Enable LPSS UARTWerner Zeh2021-10-011-0/+1
| | | | | | | | | | Enable LPSS UART for coreboot console on mc_ehl1. Change-Id: Id995953741d48fbbe2482ff7c0ef81cac5a31207 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* src/*: Specify type of `DIMM_SPD_SIZE` onceAngel Pons2021-09-031-1/+0
| | | | | | | | | | | Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once. Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer2021-08-283-12/+0
| | | | | | | | | | | | | | | | | | | | | Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/{kontron/bsl6,siemens/chili}: Add `inhibit_flashlock` nvram optionNico Huber2021-08-131-0/+1
| | | | | | | | Change-Id: I8c5d6686bf7c694f9d594e3801c79cfd7fb3da80 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56342 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl: Enable master bit in PCI config space if allowedWerner Zeh2021-08-021-1/+21
| | | | | | | | | | | | | | | | Some legacy devices need to have the master bit set in the PCI config due to old drivers not setting it correctly. Set the master bit if the feature is enabled via Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE. For now, the PCI devices with the ID 110a:403e and 110a:403f needs this master bit to be set. Change-Id: Id3f6bda97e5f47d0613a1db8f8adac0b158ab8b1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56632 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scanWerner Zeh2021-08-021-0/+30
| | | | | | | | | | | | | | | | Boards based on mc_ehl have, just like some mc_apl variants, legacy devices on the PCI bus which take longer to boot. In order to ensure that they will be enumerated correctly wait for them to come up before PCI scan starts. TEST=Checked that the new message is visible in the log. Change-Id: If2f935b69ddaa9364566deacfada5e7d41fcdabd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56631 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl1: Disable LTR for all PCIe root portsWerner Zeh2021-07-291-0/+8
| | | | | | | | | | | | | Latency Tolerance Reporting is yet another PCIe power management feature which can have a bad influence on realtime performance. Disable this feature for all PCIe root ports. Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl1: Disable L1 substates for PCIe root portsWerner Zeh2021-07-291-0/+8
| | | | | | | | | | | | | | | | L1 substates of a PCIe link are meant to save some power when the link is not active but have the drawback that the PCIe latency is increased as PLLs are switched on and off as needed. In order to get a better realtime performance, disable all substates for every PCIe root port. Change-Id: Ic5bc8410709d0f0094810bc11a7723e88c30e397 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl1: Enable Intel I210 MACPHY driverWerner Zeh2021-07-292-0/+83
| | | | | | | | | | | | This variant uses I210 MACPHYs so enable the I210 driver in order to set the needed MAC addresses. In addition add the function to retrieve a valid MAC address for the given MACPHY. Change-Id: Id1d59349db1b86cfdd71bbe27577c0530e8f0b51 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56567 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl: Enable Siemens NC-FPGA driverWerner Zeh2021-07-291-0/+2
| | | | | | | | | | | All the boards based on the mc_ehl baseboard have the NC-FPGA available. Enable the appropriate driver on baseboard level. Change-Id: I40b76a837b7ddb70ceba3135996b1c1080170c4d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56566 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl: Enable SIEMENS_HWILIBWerner Zeh2021-07-291-0/+1
| | | | | | | | | | | All variants based on mc_ehl will use the Siemens HWILIB. Select the Kconfig switch on baseboard level. Change-Id: I940f84a4a7449487fe78c793f8dbb1c1b49fa54b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56565 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl1: Enable In Band ECCWerner Zeh2021-07-291-0/+6
| | | | | | | | | | Enable IBECC for mc_ehl1 to provide a memory failure protection. Change-Id: If8f81d6bacb77dc38e231c1cedf22831de8a38a9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56564 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl1: Disable System Agent dynamic frequency supportWerner Zeh2021-07-291-1/+1
| | | | | | | | | | | In favor of better realtime performance disable dynamic frequency support in the System Agent for mc_ehl1. Change-Id: I0e62bcf2e5efa97d89bf7192f1536747a02ad992 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56563 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 23:49:05 +0000