summaryrefslogtreecommitdiffstats
path: root/src/mainboard/siemens
Commit message (Expand)AuthorAgeFilesLines
* src/mainboard/{siemens,starlabs}: Remove unused <console/console.h>Elyes HAOUAS2022-01-101-1/+0
* mb: Add space before closing comment block keywordPaul Menzel2021-12-231-1/+1
* mb/siemens/chili: Reuse options from Kconfig.nameFelix Singer2021-12-182-6/+2
* mb/siemens/mc_ehl: Enable TPM in bootblockWerner Zeh2021-12-101-0/+1
* mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCIWerner Zeh2021-11-173-0/+28
* mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetreeMario Scheithauer2021-11-151-2/+2
* mb/siemens/mc_ehl: Disable HECI #2 deviceMario Scheithauer2021-11-152-2/+0
* treewide: Replace bad uses of `find_resource`Angel Pons2021-11-041-1/+1
* mb/siemens/mc_ehl: Disable PMC low power modesWerner Zeh2021-11-041-0/+5
* mb/siemens/mc_ehl: Disable all P-StatesWerner Zeh2021-11-041-0/+3
* mb/siemens/mc_ehl: Disable C-States for CPU and packageWerner Zeh2021-11-041-0/+10
* mb/siemens/mc_ehl2: Clean up devicetreeMario Scheithauer2021-11-041-64/+4
* mb/siemens/mc_ehl: Enable Row-Hammer preventionMario Scheithauer2021-11-041-0/+3
* mb/siemens/mc_ehl2: Configure SD card detect pin in devicetreeMario Scheithauer2021-11-041-0/+3
* mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetreeMario Scheithauer2021-11-041-8/+2
* mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetreeMario Scheithauer2021-11-041-13/+13
* mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetreeWerner Zeh2021-11-031-13/+13
* mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetreeWerner Zeh2021-11-021-8/+2
* mb/siemens/mc_ehl1: Clean up devicetreeWerner Zeh2021-11-021-74/+4
* mb/siemens/chili: Drop redundant Kconfig selectAngel Pons2021-10-271-1/+0
* mb/siemens/mc_ehl2: Adjust PCH serial IO settingsMario Scheithauer2021-10-141-17/+6
* mb/siemens/mc_ehl2: Adjust USB settingsMario Scheithauer2021-10-141-12/+12
* mb/siemens/mc_ehl2: Enable PCI devicesMario Scheithauer2021-10-141-4/+4
* mb/siemens/mc_ehl2: Set coreboot ready LEDMario Scheithauer2021-10-141-0/+11
* mb/siemens/mc_ehl: Remove unneeded 'half_populated' variableWerner Zeh2021-10-121-4/+1
* mb/siemens/mc_ehl: Use SPD data from HW-Info in the first placeWerner Zeh2021-10-121-3/+22
* mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer2021-10-112-0/+14
* mb/siemens/mc_ehl: Add variant_mainboard_final()Mario Scheithauer2021-10-112-0/+11
* mb/siemens/mc_ehl2: Enable LPC ComBMario Scheithauer2021-10-111-0/+1
* mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer2021-10-111-1/+0
* mb/siemens/mc_ehl2: Adjust GPIOsMario Scheithauer2021-10-111-54/+35
* mb/siemens/mc_ehl2: Disable SATA Port 0Mario Scheithauer2021-10-111-1/+1
* mb/siemens/mc_ehl2: Enable SD-CardMario Scheithauer2021-10-111-1/+1
* mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2Mario Scheithauer2021-10-111-17/+23
* mb/siemens/mc_ehl2: Update SPD for DDR4 devicesMario Scheithauer2021-10-111-3/+3
* mb/siemens/mc_ehl: Move UART_FOR_CONSOLE switch to variant levelWerner Zeh2021-10-013-5/+8
* mb/siemens/mc_ehl: Add a new variant mc_ehl2Werner Zeh2021-10-0110-0/+605
* mb/siemens/mc_ehl1: Enable LPSS UARTWerner Zeh2021-10-011-0/+1
* src/*: Specify type of `DIMM_SPD_SIZE` onceAngel Pons2021-09-031-1/+0
* soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer2021-08-283-12/+0
* mb/{kontron/bsl6,siemens/chili}: Add `inhibit_flashlock` nvram optionNico Huber2021-08-131-0/+1
* mb/siemens/mc_ehl: Enable master bit in PCI config space if allowedWerner Zeh2021-08-021-1/+21
* mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scanWerner Zeh2021-08-021-0/+30
* mb/siemens/mc_ehl1: Disable LTR for all PCIe root portsWerner Zeh2021-07-291-0/+8
* mb/siemens/mc_ehl1: Disable L1 substates for PCIe root portsWerner Zeh2021-07-291-0/+8
* mb/siemens/mc_ehl1: Enable Intel I210 MACPHY driverWerner Zeh2021-07-292-0/+83
* mb/siemens/mc_ehl: Enable Siemens NC-FPGA driverWerner Zeh2021-07-291-0/+2
* mb/siemens/mc_ehl: Enable SIEMENS_HWILIBWerner Zeh2021-07-291-0/+1
* mb/siemens/mc_ehl1: Enable In Band ECCWerner Zeh2021-07-291-0/+6
* mb/siemens/mc_ehl1: Disable System Agent dynamic frequency supportWerner Zeh2021-07-291-1/+1