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* mb/starlabs/lite: Add support for VBOOTSean Rhodes2022-07-254-0/+44
| | | | | | | | | | | Add the required files to support VBOOT for when it is enabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I083107b21c23f42193fc88aa174ec22850f45bc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65705 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/starlabs/lite: Simplify the flash layoutSean Rhodes2022-07-221-99/+53
| | | | | | | | | | Remove the sections that coreboot doesn't need to know about. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ide6c0d44f1f9ad9b962d2b8e14ac91e87f5ca031 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65453 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/lite/{glk/glkr}: Remove Bluetooth USB portSean Rhodes2022-07-132-7/+1
| | | | | | | | | | | This reverts commit 0225af3c2ba661de82e15f163258605917ca28cf as it has no effect as the USB interface is configured by FSP S. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I20ca355eb1e088d7a7c8eacbc888ffc90833194b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/starlabs: Rename LabTop to StarBookSean Rhodes2022-07-0746-9/+9
| | | | | | | | | | | | | The LabTop was renamed to StarBook since the release of the Mk V. This change keeps the directory name more relevant, as there are more boards using the name StarBook. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3513fb56c1adf663ed7bcdade2cc52cd8c0d6f4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65640 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* 3rdparty/blobs: Advance submodule pointerSean Rhodes2022-07-071-1/+1
| | | | | | | | | | | | | | | | | | | This contains the following commits: * d55c315 mb/starlabs: Remove padding from logo * 6412d38 mb/starlabs/starbook/cml: Update EC from 1.03 to 1.07 * fb72ac5 mb/starlabs/starbook/tgl: Update EC from 1.00 to 1.03 * cda5eaa mb/starlabs: Rename labtop to starbook * f16020a Revert "soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215… This also changes starlabs/labtop Kconfig to use the new paths for the EC binaries from the above commits. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I83143118af422276ee335ad4ef9eca76f54a9fc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/starlabs/labtop/tgl: Nit - minor format changeSean Rhodes2022-07-051-7/+7
| | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I068c6e46d85d869afc72280509a03d5ff682b917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65618 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/labtop: Define CCD Port in KconfigSean Rhodes2022-07-057-14/+16
| | | | | | | | | | | | | | | | Define the CCD (aka "Webcam") USB port in the devicetree as it is used in multiple places. It is used in devtree to disable it based on the CMOS setting "webcam", and in the devicetree to configure the port tuning. This also corrects the port that is disabled on CML, from usb2_port[6] to usb2_port[3]. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I16e368fc7965f978f2302633122ba63038603c1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64704 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/labtop/tgl: Organise USB ports by hardware portSean Rhodes2022-07-051-13/+8
| | | | | | | | | | | | | Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. This also removes usb3_port[2] as it is not connected and fixes the labelling of usb3_port[0] and usb3_port[1]. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7923fc00c36687a7f89d863eb0ea4e01a036502d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/lite/glk: Update VbtSean Rhodes2022-07-051-0/+0
| | | | | | | | | | | Update the Vbt to disable the fixed mode feature, to allow for bootloader resolutions higher than 1920x1080. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibd9850dcaef97a58c6694ee594014e9f16ae7f96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/lite/{glk/glkr}: Disable UFS deviceSean Rhodes2022-06-222-0/+2
| | | | | | | | | | Disable 1d.0 UFS as it is not used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib392bc64db440ea3d98ee62536d5395587a3f6aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/lite/{glk/glkr}: Disable Sata Port 1Sean Rhodes2022-06-212-2/+0
| | | | | | | | | | Disable Sata Port 1 as it is not used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I93ecdaba5d1ce96ddcf3695edd7fb109054743e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/starlabs/lite/glkr: Don't configure GPIO's 147 through 156Sean Rhodes2022-06-211-23/+11
| | | | | | | | | | These are configured by the TXE, so they do not need to be configured. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I13957992d637a53203b4328e39c0e6607e017891 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite/glkr: Simplify GPIO macro'sSean Rhodes2022-06-211-122/+71
| | | | | | | | | | Use shorter macro's to conifgure GPIO's. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I926aac8679f847cd963be07786e9fe2e4c63bda6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite/glkr: Disconnect unused GPIO'sSean Rhodes2022-06-211-161/+151
| | | | | | | | | | | | Disconnect GPIO's that are unused, or not connected. Also update comments that are vague or have errors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1b071ec1d194f76ee78066396bac8dfff5ec851b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64651 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake: Hook Up SataPortEnable to devicetreeSean Rhodes2022-06-202-2/+8
| | | | | | | | | | | | Hook Up SataPortsEnable to the devicetree. As the default value is 0, set both [0] and [1] in all mainboards so they aren't affected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/labtop: Configure tcc_offset based on power_profile settingsSean Rhodes2022-06-204-29/+29
| | | | | | | | | | | Set tcc_offset value based on the power_profile value, ranging from 10 to 20 degrees. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I66fb266c1730833ff6e2dbf8ea39f23ee0878590 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite/glk: Organise USB ports by hardware portSean Rhodes2022-06-201-9/+7
| | | | | | | | | | | | | Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. This change also corrects the daughterboard USB 3.0 port number. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib6a934a1e5e65fe387c63b78cbe80e45e97e0a8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/lite/glkr: Correct the daughterboard USB 3.0 port numberSean Rhodes2022-06-201-1/+1
| | | | | | | | | | | | | | The daughterboard USB 3.0 was set to port 3, which is incorrect. This patch corrects that to port 4. This fixes an issue where USB 3.0 devices are not detected when plugged in to this port. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50f86dee1b512d0dd20d07e3ee17ebfa5e537bc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite/glkr: Correct USB port numbersSean Rhodes2022-06-201-2/+2
| | | | | | | | | | | | The USB ports for the Motherboard USB 3.0 and Type-C were labelled incorrectly. This change swaps the ports, so they are labelled correctly and also corrects the over-current pins that they use. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I80484dc8bdd68dd72b3848720c790d59237a9f8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite/glkr: Organise USB ports by hardware portSean Rhodes2022-06-201-8/+7
| | | | | | | | | | | Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a7f50ca2b2001e83211e8eba56bfa929ecdfd74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite: Enable enhanced C-statesSean Rhodes2022-06-202-0/+4
| | | | | | | | | | | Tested on the StarLite Mk III & Mk IV with Zorin 16.2 Core. This resulted in a reduction in power consumption of approximately 3%. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b5f4e01bc786db02184b722c74fda7d0ca055be Reviewed-on: https://review.coreboot.org/c/coreboot/+/64709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite: Configure MMIO window for ECSean Rhodes2022-06-201-0/+4
| | | | | | | | | | | The Nuvoton EC requires a window to be opened for updates, so open this window only if the Nuvoton EC is present. Change-Id: Iaa45aa58749c4d0bfc77e60b52eab2bcb270f3ee Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/labtop/kbl: Organise USB ports by hardware portSean Rhodes2022-06-201-10/+9
| | | | | | | | | | | Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib5fec81a7a04f2f5ab13784435944601902904d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/labtop/cml: Organise USB ports by hardware portSean Rhodes2022-06-201-9/+8
| | | | | | | | | | | Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie9bc6b3e20dddeb14cea195ef9a719432f66c6e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite/glk: Configure LPC IO registersSean Rhodes2022-06-201-0/+3
| | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I47523fae8d1cb0fbb972a82c43a992c9fb606ed4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite/glkr: Configure LPC IO registersSean Rhodes2022-06-201-0/+3
| | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2d949af0086c231e27ac889c0aabd0d3e00c94fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite: Disable Burst in Power Saver profileSean Rhodes2022-06-091-0/+2
| | | | | | | | | | | When the CMOS option `power_profile` is set to Power Saver, disable Burst. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4d9367306b3c0e83252cea3ee4c2733c8729d10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/lite/glk: Don't configure GPIO's 147 through 156Sean Rhodes2022-05-311-24/+1
| | | | | | | | | | These are configured by the TXE, so they do not need to be configured. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia1bf4e32aa156a0e1a74df2f62eb31cdadb376a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/starlabs/lite/glk: Simplify GPIO macrosSean Rhodes2022-05-311-111/+53
| | | | | | | | | | Use shorter macros to configure GPIOs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I91961658dca0902080576134e63e6d8a7c78d711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/starlabs/lite/glk: Disconnect unused GPIOsSean Rhodes2022-05-311-78/+61
| | | | | | | | | | | | Disconnect GPIOs that are unused or not connected. Also, update comments that are vague or have errors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic83797b8a8e05eed99db0356f360a329f6fbf347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/starlabs/lite/{glk/glkr}: Configure prt0_gpioSean Rhodes2022-05-312-0/+4
| | | | | | | | | | | PERST_0 is not used, so set this to GPIO_PRT0_UDEF (undefined) to ensure that an undefined address is not added to GNVS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iac9b116b2fa28824a89db28911188364dc9a1a53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/starlabs/lite/glk: Remove unnecessary DPTF UPDSean Rhodes2022-05-281-2/+0
| | | | | | | | | | | The default for DPTF is off (0), so remove the entry that sets this to off. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0397ff6f71766a2f738ab2b71be298ef8f2b1c9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/starlabs/lite/{glk/glkr}: Remove unnecessary parametersSean Rhodes2022-05-282-70/+0
| | | | | | | | | | | Since using FSP 2.2.0.0, the defaults match the required settings so they no longer need to be specified. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie0e00cae67cb89b184392e97b8ec196d45ea5d91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/labtop: Add LabTop Mk IIISean Rhodes2022-05-2814-1/+876
| | | | | | | | | | | | | | | | | | | Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/labtop-mk-iii-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ben McMillen <ben@starlabs.systems>
* mb/starlabs/lite: Add Bluetooth USB interfaceSean Rhodes2022-05-282-0/+4
| | | | | | | | | | Enable the USB port that is used by the Bluetooth interface on the CNVI. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a330618c5f1c5fd5e3147cb6307c157b28070ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/64545 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/lite: Remove webcam USB port from devicetreeSean Rhodes2022-05-284-6/+6
| | | | | | | | | | | Remove the Webcam USB port form the devicetree and handle it solely in devtree, which will enable or disable it based on the CMOS option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c89c7103aca5c3d42215122e9d94c83947b6fee Reviewed-on: https://review.coreboot.org/c/coreboot/+/64544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/starlite/lite: Configure tcc_offset based on power_profile settingsSean Rhodes2022-05-281-6/+9
| | | | | | | | | | | Set tcc_offset value based on the power_profile value, ranging from 5 to 15 degrees. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id30bec9c095517884a7361226aed703b370f2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/lite/{glk/glkr}: Disable PMC PCI deviceSean Rhodes2022-05-282-2/+2
| | | | | | | | | | | | | | The PMC is accessed via sideband registers, so the PCI device is not needed. Disabling it solves a bug where the laptop cannot be powered on without the charger connected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I78f4aa4567dfc154ef5cb21f8746265259cd53e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64451 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/lite/{glk/glkr}: Disable DPTF deviceSean Rhodes2022-05-282-2/+2
| | | | | | | | | | DPTF is not used, so disable the corresponding PCI device. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9e4a3bada13dcabc1af3e1e5b3c215939f8239fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/starlabs/lite/{glk/glkr}: Remove subsystem device IDSean Rhodes2022-05-282-6/+2
| | | | | | | | | | | | Remove the subsystem device ID for HDA devices, so that the correct Intel [8086:xxxx] is used. This was an old workaround for Windows that is no longer required with a new driver. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I63d6a4b0f19d400d683cab5dacca787d6c6a0fdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/lite/{glk/glkr}: Decrease S3 assertion time to 28 msSean Rhodes2022-05-282-2/+2
| | | | | | | | | | | Set S3 assertion time to 28000us as this is sufficient time for rails to discharge. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4a14e7b30bb1fc4c0c1d3ff2f75069863458487f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64447 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/lite/glkr: Correct OverCurrent PinSean Rhodes2022-05-281-6/+6
| | | | | | | | | | | | The USB ports use both OC0 and OC1. Whilst they work perfectly with OC_SKIP, set them to the correct pins. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If173b443d9770083d76519b854b513d8e47b9e71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite/glk: Correct OverCurrent PinSean Rhodes2022-05-281-8/+8
| | | | | | | | | | | | | | The OC pin was set to 0, which isn't connected. All USB ports are connected to OC1. This solves a strange issue where the Lite can't be powered on without the charger connected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I700ddde291f0e4be6e3787e2da13f6d3ece736b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* soc/intel/tigerlake: Hook up FSP hyper-threading setting to option APIFelix Singer2022-05-261-4/+0
| | | | | | | | | | | | | | | | | Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the mainboard starlabs/laptop/tgl, since it is obsolete now. Change-Id: I49bbd4a776b4e6c55cb373bbf88a3ca076342e3e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* soc/intel/cannonlake: Hook up FSP hyper-threading setting to option APIFelix Singer2022-05-261-4/+0
| | | | | | | | | | | | | | | | | | | | | Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the following mainboards, since it is obsolete now. * siemens/chili * starlabs/laptop/cml Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/starlabs/lite/glk: Correct indendation in devicetreeSean Rhodes2022-05-211-2/+3
| | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I780e2765059ad7473fe5f33c50dd0d8a561151fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/starlabs/labtop: Enable Max Charge for CMLSean Rhodes2022-05-121-0/+1
| | | | | | | | | | | Enable the max charge feature for cml, as the EC supports it since Star Labs EC firmware 1.06. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I779a686960b63025fb5f40e826ed117f402a0b2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64093 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/lite: Change PMC from hidden to onStephen Edworthy2022-05-062-2/+2
| | | | | | | | | | | | | | With the PMC set to hidden, on certain Operating Systems, including ZorinOS 16 and Manjaro 21.2.5, it would get stuck at a black screen when exiting from S3. With the PMC set to on, this issue no longer occurs. Signed-off-by: Stephen Edworthy <stephen@starlabs.systems> Change-Id: I0cf1be7f6919d974614f2196a0eb611cc40abe3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* tpm: Refactor TPM Kconfig dimensionsJes B. Klinke2022-04-212-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/starlabs/labtop: Remove subsystem device IDSean Rhodes2022-04-062-2/+0
| | | | | | | | | | | | Remove the subsystem device ID for HDA devices, so that the correct Intel [8086:xxxx] is used. This was an old workaround for Windows that is no longer required with a new driver. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50c03a2df06af3ef1939afd0739e083a9056557f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 11:59:37 +0000