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* mb/starlabs/starbook: Always include the tcss.aslSean Rhodes2024-02-191-2/+0
| | | | | | | | | | | The tcss.asl doesn't just relate to tcss, it is required for core scheduling, so include it for all platforms. Change-Id: I781ba8756e06133799e8d6d91302968cc3ea0a56 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80485 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tigerlake: Drop redundant PcieRpEnableNico Huber2024-02-191-1/+0
| | | | | | | | | | | | | | | The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*: Add SPDX headers for cmos.default filesMartin Roth2024-02-184-0/+8
| | | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib7beed7218f317bc2352b65a6191ef1cdaa0742d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* mb/samsung to mb/up: Add SPDX license headers to Kconfig filesMartin Roth2024-02-186-0/+12
| | | | | | | | Change-Id: Ied455ff29b151fb5f4bca26a189b1d4104d8cede Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80595 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/rpl: Configure PMC muxSean Rhodes2024-02-151-0/+11
| | | | | | | | | | | | | | Configure PMC mux in devicetree. This allows PD controllers to be used for both video and power delivery. Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD display can supply power and display video output. Change-Id: I580b148b036e62fbcab50d1ca2ab1ed021cfed6b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/adl: Configure PMC muxSean Rhodes2024-02-151-0/+11
| | | | | | | | | | | | | | Configure PMC mux in devicetree. This allows PD controllers to be used for both video and power delivery. Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD display can supply power and display video output. Change-Id: I9e49612d7f165a9c9604093535f7b141a4c7048c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79426 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/kbl: Remove tcc_offset entrySean Rhodes2024-02-141-3/+0
| | | | | | | | | | | The TCC offset is configured in devtree.c, so remove it from the devicetree. Change-Id: I044a68854cc142b057cf31b4e2456d2ad1d0dd3a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/lenovo to mb/squared: Rename Makefiles from .inc to .mkMartin Roth2024-01-2410-0/+0
| | | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4790adb41cb62c8c8dd44261a2926dfb6350955a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80111 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* mb/starlabs/starbook/cml: Use chipset dt reference namesFelix Singer2024-01-191-49/+49
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Ia004de6606a1685822d5567123887c60d89e3119 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/starlabs/starbook/rpl: Enable C1eSean Rhodes2024-01-111-0/+1
| | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3a317d031e71f86afc50b229d1b97197552f4fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/starlabs/starbook/kbl: Use chipset dt reference name for LPCFelix Singer2023-11-131-1/+1
| | | | | | | | Change-Id: I41b3ed4926fe77c5729672fd7a7bcb8ca0c5c216 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79033 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/*/Kconfig: Fix default power state after failureMatt DeVillier2023-10-262-4/+4
| | | | | | | | | | | | | | | | | | | | | POWER_STATE_OFF_AFTER_FAILURE can't be directly selected since it's a choice, so instead set POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n, as it's functionally equivalent. This fixes the warnings generated by the pre-commit hook Kconfig check. It is necessary to override and set default n in the mainboard Kconfig as it is set to default y in src/soc/intel/common/block/pmc/Kconfig. TEST=select starlabs/starbook_adl in menuconfig and verify the default power-on setting is S5/soft off. Change-Id: I3ce33517dcc0af693b8db8d1de2926117ad3c16b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78627 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/starlabs/starbook/{adl,rpl}: Disable GpioOverrideSean Rhodes2023-10-244-8/+10
| | | | | | | | | | | | | | | | Disable the GpioOverride UPD in FSP M, and comment out the Clock Request GPIOs to ensure that coreboot doesn't touch them. This solves behaviour that can only be described as weird: * Devices connected to Root Ports don't initialise * Hang seen when entering S5 * Hang when edk2 is reached Change-Id: Idf8d2112a1c44064af73bb54fd3e1a1a429e0649 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs: Set POWER_STATE_OFF_AFTER_FAILURESean Rhodes2023-10-202-0/+7
| | | | | | | | | | | | | | | This Kconfig option is used as a failback when `get_uint_option` fails. It will fail after coreboot is flashed, as the cfr code has not yet setup the options. Change the default to OFF, so when it does fallback, it's the correct behaviour. Change-Id: I5d06047fe23322520e9c84ded8f1941f6d716a51 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook: Include ACPI for GNA scoring acceleratorSean Rhodes2023-10-201-0/+2
| | | | | | | | Change-Id: Id42d07aabfd08c6c7a38515f9cf4b749750deecd Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78202 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/adl: Enable PchHdaSdiEnableSean Rhodes2023-10-201-0/+1
| | | | | | | | | | This is required for the HDA device to work. Change-Id: I5fd3617c4cb1e69b7e0ecf6cddf4c143da99b927 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78201 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/{adl,rpl}: Remove unnecessary entriesSean Rhodes2023-10-042-2/+0
| | | | | | | | | | | Certain devices are enabled in Alder Lakes chipset.cb, so remove them from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78198 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/{adl,rpl}: Enable the CNVi deviceSean Rhodes2023-10-042-0/+14
| | | | | | | | Change-Id: I1b0052b569b575fec7893322dec0280c9f1ed79f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78197 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/rpl: Update the VBT to 251Sean Rhodes2023-10-041-0/+0
| | | | | | | | | | | | Updating FSP to v4301.01 caused a strange flicker when connecting an external display. Update the VBT to 251 from 242 with the exact same settings to resolve this. Change-Id: I36bb2cc92e744e761ec6af9c026c429373c1750a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/rpl: Enable the PD interrupt GPIOSean Rhodes2023-09-081-2/+2
| | | | | | | | | | | Enable the PD interrupt GPIO, GPP_B11, so that HPD works when Thunderbolt is disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie37976d58921b7a12dff16d93d7ac9bdd92edbea Reviewed-on: https://review.coreboot.org/c/coreboot/+/77673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/starlabs/starbook/rpl: Correct GPP_A19Sean Rhodes2023-09-081-2/+2
| | | | | | | | | | | A19 was incorrectly labelled as TCP0 HPD. It is not connected so configure it accordingly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5aea723c2e8c0758d413bbc4bfd0ce92b22d0c87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/starlabs/starbook/{adl,rpl}: Remove unnecessary entriesSean Rhodes2023-09-082-4/+0
| | | | | | | | | | | Certain devices are enabled in Alder Lakes chipset.cb, so remove them from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/starlabs/starbook/rpl: Disable dynamic Tc-cold handshakeSean Rhodes2023-09-011-0/+2
| | | | | | | | | | | | With the Tc-cold handshake, there's a fast flicker when connecting external displays. With it disabled, it's just one "flick", so use this as it's lesser of two evils. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie42b935d3e69beff6a1e503a8dee69554123b4f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/rpl: Fix the Thunderbolt cmos optionSean Rhodes2023-08-173-0/+13
| | | | | | | | | | | For Thunderbolt to be disabled, `UsbTcPortEn` and `TcssXhciEn` also need to be disabled. Change-Id: Ie02c1e0ea7583bbd78e25c8184e2cdf2b6281741 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook: Add Raptor Lake StarBook Mk VI variantSean Rhodes2023-08-1111-12/+873
| | | | | | | | | | | | | | | | | | Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 22.04 * Manjaro 22 No known issues. https://starlabs.systems/pages/starbook-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7c92bf92ab4de546c3633fae7e19a302409508ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/74444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook: Add support for VBOOTSean Rhodes2023-08-107-0/+104
| | | | | | | | | | Add the required files to support VBOOT for when it is enabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I842b79d8e144414ce42b3d0d9dfd2b5180ecf70d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74230 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/adl: Update the VBTSean Rhodes2023-08-101-0/+0
| | | | | | | | | | | Adjust the Type-C output ports to "Integrated Displayport" to comply with FSP 4221. Change-Id: Ifcb4a086106f90c70926f44a7566330efd185544 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/starlabs/lite/glkr: Disable PSRSean Rhodes2023-08-101-0/+0
| | | | | | | | | | Disable PSR in the VBT to avoid flickering on kernels later than 5.15. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3640fcea73e278e6c8968a4b0c9ba7cf04a2361f Reviewed-on: https://review.coreboot.org/c/coreboot/+/77134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/starlabs/lite/glk: Disable PSRSean Rhodes2023-08-101-0/+0
| | | | | | | | | | Disable PSR in the VBT to avoid flickering on kernels later than 5.15. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5b58f4d26fa0032a5aed3af0db71a5daf41fdd8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76941 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/adl: Enable CNVi Bluetooth UPDsSean Rhodes2023-08-101-0/+3
| | | | | | | | | | | Enable "CnviBtCore" and "CnviBtAudioOffload" to increase bluetooth performance. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibafabfaa39ba46620a2e06b288c457267f041ab0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/adl: Enable the crashlog PCI deviceSean Rhodes2023-08-102-1/+1
| | | | | | | | Change-Id: I8dc97ca0fb310417a28e253f378511f510c3b4b3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77124 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/tgl: Enable the crashlog PCI deviceSean Rhodes2023-08-101-0/+1
| | | | | | | | Change-Id: I88831f56a259d45e3ae1f66abd1d7aaeac4ede20 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/tgl: Use the merlin ec codeSean Rhodes2023-08-101-1/+1
| | | | | | | | | | | | | Switch the TGL variant to use the "merlin" EC variant, and delete the no longer needed "TGL" EC variant. This is not a functional change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id4d305490b48c1c79ea52b0bbaa79b675412e0b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76332 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/adl: Use the merlin ec codeSean Rhodes2023-08-101-1/+2
| | | | | | | | | | | | | Switch the ADL variant to use the "merlin" EC variant, and delete the no longer needed "ADL" EC variant. This is not a functional change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I61e56cc95a26be60d7f10c89d26bce2d857ae81a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/adl: Correct the FMAPSean Rhodes2023-08-101-1/+1
| | | | | | | | | | Specify the size of the ME region so that it matches the IFD. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I51ba0a7646ab72d4dd22b99519708649c78b25b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/starlabs/starbook: Select VALIDATE_INTEL_DESCRIPTORSean Rhodes2023-08-101-0/+1
| | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5dac42fb2239e7bc14dbe45442cc562927973b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook: Adjust TCC Offset for all boardsSean Rhodes2023-07-282-6/+6
| | | | | | | | | | | Lower the TCC Offset by 10 degress. Change-Id: Ib80d3b73c41ec1196d8294c35b43333e0df218d5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76374 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/starlabs/*: Remove the power_on_after_fail optionSean Rhodes2023-07-068-20/+0
| | | | | | | | | | | None of these boards have an RTC battery, so this option has no effect. Remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9a55227f74c0b9ae9b56bdef4b8f53b2425b331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mainboard/starlabs/starbook: Unselect RESIZABLE_BARSSean Rhodes2023-07-061-4/+0
| | | | | | | | | | | | It is not needed, so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I606d0a76926e90e4ce321163400aa50ea961c2a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75342 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/apollolake: Switch to snake case for ModPhyIfValueMario Scheithauer2023-06-192-2/+2
| | | | | | | | | | | For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyIfValue'. Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake: Switch to snake case for DisableComplianceModeMario Scheithauer2023-06-192-2/+2
| | | | | | | | | | | For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableComplianceMode'. Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/starlabs/starbook: Fix the ramtop CMOS entrySean Rhodes2023-06-032-6/+6
| | | | | | | | | | | The ramtop entry has to be 10 bytes long, and it was incorrectly set to 10 bits, instead of 10 bytes. Change this to 80. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I506f9d98a389dd859038fd270c5e344b65f514f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75420 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake: Switch to snake case for SataPortsEnableMario Scheithauer2023-06-022-2/+2
| | | | | | | | | | | | | For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
* mb/starlabs/starbook: Add ramtop to CMOS layoutSean Rhodes2023-05-232-0/+6
| | | | | | | | | | | Add `ramtop` to CMOS layout so SOC_INTEL_COMMON_BASECODE_RAMTOP can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I88128d2c62bdc3246a3f30e768c353f0fe3faeb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/starlabs/starbook: Let coreboot configure ASPMSean Rhodes2023-04-292-25/+0
| | | | | | | | | | | | | FSP is fractionally faster at configuring ASPM (1,118,688 vs 1,122,205) but coreboot's configuration results in lower power consumption of approximately 0.5W when idling - the reason why is unknown. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib15eaede956f0aa55118d093fdff0fd9487df250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74520 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/adl: Correct the number of NID entriesSean Rhodes2023-04-281-2/+2
| | | | | | | | | | | | The number of NID entries was too high for the Realtek and Intel sound cards, preventing the verb table from loading. Now the values are correct; it loads as intended. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I79825313a4801c120a0a2a321cbabab7c728aa71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/adl: Correct port for Hot PlugSean Rhodes2023-04-281-1/+1
| | | | | | | | | | | | | | Commit 5103b87a4d7b ("mb/starlabs/starbook/adl: Add an option to enable Hot Plug") introduced an option to enable Hot Plug for the SSD. The port was set to 4 (RP5) which is the wireless card. Change this to 8 (RP9) which is the SSD. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I884f4997d73e31bd422477952466f168afad66a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74738 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORTSean Rhodes2023-04-202-2/+0
| | | | | | | | | | | | | Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is only used on `starlabs/starbook` which selects D3COLD_SUPPORT so the UPDs will not change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tigerlake: Replace SOC_INTEL_TIGERLAKE_S3 with D3COLD_SUPPORTSean Rhodes2023-04-201-1/+0
| | | | | | | | | | | | | | | The Kconfig option SOC_INTEL_TIGERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Remove it, and instead use D3COLD_SUPPORT so it's clear what the option is doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74405 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORTSean Rhodes2023-04-191-1/+3
| | | | | | | | | | | | | | | The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Rename it to D3COLD_SUPPORT to make it clear what it's doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-07 17:00:58 +0000