summaryrefslogtreecommitdiffstats
path: root/src/mainboard
Commit message (Collapse)AuthorAgeFilesLines
...
* mb/google/rex: Set audio GPIOs based on fw_configKapil Porwal2023-02-232-0/+59
| | | | | | | | | | | | | | | | | | Define some actions based on probe results for audio: - Disable the SoundWire GPIOs when I2S option is selected. - Disable the I2S GPIOs when SoundWire option is selected. - Disable all the GPIOs when no audio is enabled. BUG=b:269497731 TEST=Test that GPIOs are configured based on the current value of the fw_config field in cbi. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0ed452a0d08e6779add318d9bbd1e97b50b6aea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/rex: Use gpio padbased table overrideKapil Porwal2023-02-232-4/+17
| | | | | | | | | | | | | | | | | | | In order to improve gpio merge mechanism. Change iteration override to padbased table override. And the following patch will change fw config override with ramstage gpio table override. Port of commit 7aef2b1294f2 ("mb/google/nissa: Apply gpio padbased table override") BUG=none TEST=Verify devbeep at depthcharge console Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2ee86bbec7d25a35d726f29ad79891f1054bf52c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73182 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* intel/alderlake: remove skip_mbp_hob SOC chip configKapil Porwal2023-02-233-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for RPL & ADL-N based ChromeOS platforms. It is not disabled for ADL-P based platforms because ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Taniks. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia396b633a71aedf592c45b69063ee0528840fd2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/intel/mtlrvp: Move MX98357A codec out of soundwire nodeYong Zhi2023-02-231-9/+8
| | | | | | | | | | | | | | | MX98357A is not a soundwire codec, so move it out of drivers/intel/soundwire node. BUG=none TEST=Build and boot MTL-P RVP to Chrome OS. Verify I2S audio card enumeration and no max98357a entry under /sys/bus/soundwire/devices. Signed-off-by: Yong Zhi <yong.zhi@intel.com> Change-Id: I24fc7084ea18445c341eed012cfacde8de126fd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com>
* mb/google/skyrim/var/crystaldrift: Update devicetree settingYunlong Jia2023-02-231-1/+126
| | | | | | | | | | | | | | | | | Setup FW_Config for our project. Configure USBHub\PIXA Touchpad\Audio(rt5682s & alc1019). BRANCH=None BUG=b:262798445, b:268621319 TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I2c590ae36d4d089f70e1799189cd414f825e5b8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/*: Resume from suspend on critical batteryIvan Chen2023-02-225-17/+31
| | | | | | | | | | | | | | | | | | | | | This patch makes EC wake up AP from s3/s0ix for OS shutdown/hibernate when the state of charge drops to low_battery_shutdown_percent. BUG=b:255465618 TEST=emerge-nissa chromeos-bootimage (EC: https://crrev.com/c/4243898) Verify system resumes from s0ix and then enter S5 on nivviks with steps: 1. disconnect AC 2. powerd_dbus_suspend --disable_dark_resume=false 3. fakebatt 5 4. fakebatt 4 Change-Id: I63b5246432687e38ddfc5733ac3a115c3456d7e9 Signed-off-by: Ivan Chen <yulunchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73082 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* Revert "mb/google/poppy: Nami - invoke power cycle of FPMCU on startup"Subrata Banik2023-02-222-75/+4
| | | | | | | | | | | | | | | | | | | | This reverts commit 2e6fa8206e0a3bdd2e53542b6377fe2b37e3f26e. Reason for revert: causing `redefinition` issue. src/mainboard/google/poppy/variants/nami/gpio.c:527:26: error: redefinition of 'variant_romstage_gpio_table' const struct pad_config *variant_romstage_gpio_table(size_t *num) ^ src/mainboard/google/poppy/variants/nami/gpio.c:426:26: note: previous definition is here const struct pad_config *variant_romstage_gpio_table(size_t *num) ^ Change-Id: I107cce8bf3a5bf38edb39b9d46512ee0d467d354 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73210 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/google/dedede/var/dibbi: Enable USB2 port 6Sam McNally2023-02-221-0/+1
| | | | | | | | | | | | | | | | | USB2 port 6 may be used for a PL2303 USB to UART bridge, so enable the port. BUG=b:269690930 TEST=kernel can detect a PL2303 USB device BRANCH=dedede Change-Id: I0ba421c3a502e69d101de40bbd31122211d3fb05 Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
* mb/google/poppy: Nami - invoke power cycle of FPMCU on startupTarun Tuli2023-02-222-4/+75
| | | | | | | | | | | | | | | | | | | | | | Add functionality such that the FPMCU is power cycled long enough on boot to ensure proper reset. This solution relies solely on coreboot to sequence the power and reset signals appropriately (150ms on boot). BUG=b:245954151 TEST=Confirmed FPMCU is still functional on Nami. Confirmed power is off for 150ms seconds on boot. Confirmed RCC_CSR of FPMCU indicates power cycle occurred. Confirmed reset is de-asserted approx 3ms after power application (target >2.5ms) Change-Id: I21eb85dc11e0ea0eb5de8a6092b01663d3c3df91 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68820 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/skyrim/var/markarth: Update Elan touchscreen power sequenceJohn Su2023-02-211-1/+1
| | | | | | | | | | | | | | | | Based on product spec v1.4, update T3 timing from 180 ms to 150 ms. BRANCH=none BUG=b:262734395 TEST=emerge-skyrim coreboot chromeos-bootimage Then the Elan touchscreen works fine. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I0d8f1e008276fccdfbb8c76cfebaccbe71160b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73130 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* mb/google/brya/var/skolas: remove disable_package_c_state_demotionNick Vaccaro2023-02-201-4/+0
| | | | | | | | | | | | | | | | Package C state demotion is now disabled for all RPL SoCs from within soc/intel/alderlake/fsp_params, so no need to duplicate that in the skolas devicetree.cb. BUG=268296760 BRANCH=firmware-brya-14505.B TEST=Boot and verified that S0ix issue is resolved. Change-Id: I1c630e2efbdddd18a5423c79b73269e9b1be79c7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORTSean Rhodes2023-02-203-4/+2
| | | | | | | | | | | Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive` so their configurations are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Remove useless "_STA: Status" commentElyes Haouas2023-02-1918-42/+42
| | | | | | | | | Change-Id: I99ded00fa6dadb494c1523d00063dbc1fde95614 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73093 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Report SKU ID and panel ID for unprovisioned devicesYidi Lin2023-02-181-3/+8
| | | | | | | | | | | | | | | | To make MIPI/eDP panel functional on unprovisioned devices, it requires passing SKU ID and panel ID info to the payload(depthcharge) to load the corresponded device tree for kernel. BUG=b:247415660 TEST=cbmem -1 |grep "SKU Code". Change-Id: Id2254729b7bd621d1e9bc520e8f40916d0f81030 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73076 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/protectli/vault_cml: Disable PTT and SPI TPMMichał Żygowski2023-02-171-0/+93
| | | | | | | | | | | | | | | | The platform supports a discrete LPC TPM module. However, ME firmware enables PTT by default and descriptor is configured for SPI TPM on the platform's original firmware. So disabling PTT in ME is not enough, because it falls back to SPI TPM. Ensure PTT is disabled in ME and SPI TPM is disabled in descriptor soft straps. TEST=Boot VP4650 and see LPC TPM is recognized by coreboot. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3764e085f2eb5ae957b9087d150320def7af4fc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* mb/protectli/vault_cml: Add Comet Lake 6 port board supportMichał Żygowski2023-02-1721-0/+1126
| | | | | | | | Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* mb/google/skyrim/var/frostflow: Update Elan touchscreen power sequenceFrank Wu2023-02-171-1/+1
| | | | | | | | | | | | | | | | | Based on product spec v1.4, update T3 timing to 150 ms from 300 ms BRANCH=none BUG=b:269041202 TEST=emerge-skyrim coreboot chromeos-bootimage Then the Elan touchscreen works fine. Change-Id: Ie5bd4bc2c8be2e43470edd374af0623162067497 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Chao Gui <chaogui@google.com>
* tree: Use __func__ instead of hard-coded namesElyes Haouas2023-02-177-9/+9
| | | | | | | | Change-Id: I87e383ce2f28340dbc3c843dbf2ed0e47c00a723 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/roda/rv11: Remove unuseful "_ALR: Ambient Light Response"Elyes Haouas2023-02-171-1/+1
| | | | | | | | Change-Id: I3a846d8e4b70ccb3e6fde448c00376cd0088716c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/rodarv11: Remove unuseful "_ALI: Ambient Light Illuminance"Elyes Haouas2023-02-171-1/+1
| | | | | | | | Change-Id: I0cbdcd5a787d99e2579a312a51c63d7fc4120462 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* treewide: Remove unuseful "_AEI: ACPI Event Interrupts"Elyes Haouas2023-02-173-3/+3
| | | | | | | | Change-Id: I58a4e4fbd1a43462147daa58a5fda767cfd59c06 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* treewide: Remove unuseful "_ADR: Address" commentElyes Haouas2023-02-177-7/+7
| | | | | | | | | Change-Id: Ib968fe7f9f95e8f690b46b868fd7d6f9332b4c9a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72664 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* treewide: Remove unuseful "_UID: Unique ID" commentElyes Haouas2023-02-1714-32/+32
| | | | | | | | Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* treewide: Remove unuseful "_CID: Compatible ID" commentElyes Haouas2023-02-172-2/+2
| | | | | | | | Change-Id: I7db69e2faf412b9c6732f6dfc362d5774094ef27 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas2023-02-1721-41/+41
| | | | | | | | | | Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/hp/z220_series: Reorder Kconfig selects alphabeticallyFelix Singer2023-02-171-13/+13
| | | | | | | | | Change-Id: I4035fabd46b1ba7fa5463abb7f780aeccd6a96e0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/google/dedede/var/dibbi: Update devicetree for enabling audioSam McNally2023-02-171-1/+2
| | | | | | | | | | | | | | | | Enable HDA device and update jack codec HID from ALC5682I-VD to ALC5682I-VS. BUG=b:268309238 TEST=kernel detects audio DSP and rt5682s BRANCH=dedede Change-Id: Icd17d5009ab8ef4711bb6c5fa414a8188fc0912f Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/nissa/yaviks: Tuning eMMC DLL value for eMMC initialization errorchia-ling.hou2023-02-171-0/+45
| | | | | | | | | | | | | | BUG=b:265611305 TEST=Reboot test 2500 times pass Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Change-Id: I2b114cac58a7fadeaee6d48996cb8b51f192e78f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/scaleway/tagada: Drop supportFelix Singer2023-02-1621-1801/+0
| | | | | | | | | | | | | | | | | | | | According to the author of the mainboard scaleway/tagada, the mainboard is not used anymore. Since the mainboard is not publicly available for purchase and not used anywhere else, the usual deprecation process of 6 months is not needed. Thus, to reduce the maintenance overhead for the community, support for the following components will be removed from the master branch and will be maintained on the release 4.19 branch. Also, add a note to the 4.20 release notes. * Mainboard Scaleway Tagada Change-Id: Ifb83b8f2b1dc40cbef657e52c629948dc466ec6e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72915 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Add new baseboard hades with variants hadesEric Lai2023-02-1612-0/+303
| | | | | | | | | | | | | | | | | Add a new baseboard for hades, an Intel RPL based reference design. Also, add variants for the reference boards hades. This commit is a stub which only adds the minimum code needed for a successful build. Need update gpio and memory DQ pins after final shchematic comes out. BUG=b:269371363 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib7fbdf997df8225cc7814a34f8b4e4e04884dbf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/geralt: Pass XHCI_INIT_DONE to the payloadYidi Lin2023-02-161-0/+1
| | | | | | | | | | | | | BUG=b:269059211 BRANCH=none TEST=emerge-gralt coreboot Change-Id: Ia2ec6db332939f1ac629cda9a0784a12c92d91da Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73056 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
* mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1Cliff Huang2023-02-162-4/+4
| | | | | | | | | | | | | | | Fix RTD3 timing for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec. BUG=none BRANCH=firmware-brya-14505.B TEST=Insert a SD card or NIC AIC on PCIe slot1 and run 'suspend_stress_test -c 1'. The RP8 should not cause suspend issue. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72422 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/birman&mayan: Use relative address as EC FW locationZheng Bao2023-02-162-12/+2
| | | | | | | | | | | | | | | | | | | When the flash size is over 16M, the absolute address could be lager than 16M, which can not be taken by CBFS. For the relative address, it is more flexible. This is one of series of patches to support 32/64M flash. BUG=b:255374782 TEST=binary identical test on birman and mayan when CONFIG_BIRMAN_HAVE_MCHP_FW and CONFIG_MAYAN_HAVE_MCHP_FW are set as y. Change-Id: I65be3039cd3449bfb481ad87281b72e88a58bd45 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* mb/ocp/deltalake: Set SMM console log level via VPDJohnny Lin2023-02-162-0/+5
| | | | | | | | | | | | | Select DEBUG_SMI and RUNTIME_CONFIGURABLE_SMM_LOGLEVEL. Tested=On OCP Delta Lake, SMM log level can be changed via VPD variable. Change-Id: I73afc944fbd6c21e884397f3049bd363e2c1ce2c Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47006 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* mb/google/rex: Mark unused USB ports as emptySubrata Banik2023-02-161-0/+19
| | | | | | | | | | | | | | | | | | | | This patch marks unused USB ports (USB2.0/TCSS) empty to avoid prompting wrong dmesg as below. ``` usb usb2-port3: Cannot enable. Maybe the USB cable is bad? ``` Mainboard variants to override the USB ports as per the target board design. TEST=Able to build and boot google/rex with all USB ports are working as expected. Change-Id: Ic3d21151a22f2318413f480f3386bf2dbf696307 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brask/var/aurash: Initiate coreboot settingZoey Wu2023-02-167-2/+628
| | | | | | | | | | | | | | | | | | | | Initial Aurash configuration base on moli design. 1. Set up gpio. 2. Add memory config. 3. There is no SD card setting on aurash, remove it from overridetree. 4. Follow moli psys schematic design. 5. Enable BT offload. BUG=b:269063331 TEST=emerge-brask coreboot. Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: Ia9088cc2937bab72c8c22af592392384a10616a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ricky Chang <rickytlchang@google.com>
* mb/hp/snb_ivb_laptops: Clean up USBDEBUG_HCD_INDEX settingFelix Singer2023-02-151-6/+2
| | | | | | | | Change-Id: Iab21376d1887b0c79ea463885520781d042b040d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* mb/google/brya/var/omnigul: Add memory parts supportJamie Chen2023-02-153-1/+3
| | | | | | | | | | | | | | | | | | | | | | Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1) Samsung K3KL8L80CM-MGCT 2) Hynix H58G56BK7BX068 3) Micron MT62F1G32D2DS-026 WT:B 4) Micron MT62F512M32D2DR-031 WT:B 5) Hynix H58G56BK8BX068 BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I1f650c7e90804e871572f42ac925da85afd7f9d3 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72886 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com>
* mb/intel/mtlrvp: Enable mipi_camera for MTL-P RVPUsha P2023-02-152-2/+117
| | | | | | | | | | | | | | | | | | | | | | | | Add support for MTL-P RVP mipi camera functionality BUG=None TEST=Build and boot MTL-P RVP to Chrome OS. Verify SSDT entries related to mipi camera and verify camera working. Scope (\_SB.PCI0.I2C1) { Device (CAM0) Scope (\_SB.PCI0.I2C0) { Device (CAM1) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I698edd7155fc38477f3416900799e61d3295fd1a Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Harsha B R <harsha.b.r@intel.com>
* mb/intel/mtlrvp: Enable Audio for MTL-P RVPUsha P2023-02-153-1/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds FW_CONFIG and codec support for MTL-P RVP BUG=None TEST=Build and boot MTL-P RVP to Chrome OS. Verify audio codec listed under aplay -l and audio working with the connected audio card. localhost ~ # aplay -l **** List of PLAYBACK Hardware Devices **** card 0: sofrt5682 [sof-rt5682], device 0: Headset (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 1: Speakers (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 5: HDMI1 (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 6: HDMI2 (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 7: HDMI3 (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 8: HDMI4 (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Ib29ac3e4105e578e1555076d180b35a8265a99c8 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/asrock/b75pro3-m: Reorder Kconfig selects alphabeticallyFelix Singer2023-02-151-3/+3
| | | | | | | | | | | Built asrock/b75pro3-m with BUILD_TIMELESS=1 and coreboot.rom remains the same. Change-Id: I8db6b870f2d4aac35766717866b519921d270f9e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* mb/amd/chausie,mayan: Use common missing APCB warningFred Reitberger2023-02-152-2/+2
| | | | | | | | | | | Use the common missing APCB warning when the APCB is missing Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie6303bc3457731bcac322770c4c08712f89fce3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common: Move missing APCB warning to common areaFred Reitberger2023-02-151-6/+0
| | | | | | | | | | | | | Move missing APCB warning from birman to amd/common so that other mainboards can utilize the same warnings if the APCB is missing. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I7ae689726ae4f7ccdf6959e47cbb5aee15cdb690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/brask/var/constitution: update gpio settingsMorris Hsu2023-02-152-0/+163
| | | | | | | | | | | | Configure GPIOs according to schematics TEST=emerge-brask coreboot Change-Id: Ib27f1c334cad47b3be57f57b7cc8ca5530118328 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72945 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/agah: Adjust i2c1 and i2c2 timing Parameters for 400KHzTarun Tuli2023-02-151-0/+6
| | | | | | | | | | | | | | | | | Adjust timing parameters on i2c1 and i2c2 to meet timing requirements. For SCL, the t-high time is now over the min 600ns requirement for 400KHz operation (measure at over 700ns). Also, this change does not violate other parameters - rise time, setup time and hold time. BUG=b:264704732 TEST=Verified all timings meet spec now Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/acpi: Update checksum in NVPCF DSM subfunctionTarun Tuli2023-02-151-1/+1
| | | | | | | | | | | | | | | The NVPCF DSM subfunction specified a incorrect checksum. Update this function to the proper checksum of 0xaf. BUG=b:214581372 TEST=build Change-Id: Ib58bd6cc10703ca67a7a4f520273865a95a4702b Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/intel/mtlrvp: Enable S0ixUsha P2023-02-151-0/+3
| | | | | | | | | | | | | | | | | This patch enables S0ix for MTL-P RVP platform BUG=None TEST=Able to enter low power idle S0 on MTL-P RVP Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Id84f21d81197e44d6dd0dd8888c80848aa3679e0 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71994 Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
* Revert "mb/google/brya/vell: Add PS1/PS2 cutoff point"Shon Wang2023-02-151-8/+0
| | | | | | | | | | | | | | | | | This reverts commit e30695dbe196ea42864ad03af799706eaae11f02. for meet thermal criteria, modify PS1/PS2 cutoff to default value BUG=b:229803757 BRANCH=brya TEST='FW_NAME=vell emerge-brya coreboot' Change-Id: Ie009788116f1e25db8aed2df58102a316a8aeef2 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72833 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Add Kconfig for TPM I2C busZoey Wu2023-02-151-0/+1
| | | | | | | | | | | | | Add TPM I2C for aurash to avoid TPM I2C fail. BUG=b:269050049 TEST=emerge-brask coreboot. Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: I1947d2e1189f46d8dab01837f75de7cb6e9e0579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/skyrim: Create whiterun variantIsaac Lee2023-02-1410-0/+481
| | | | | | | | | | | | | | | | Create the whiterun variant of the skyrim reference board by copying the winterhold files to a new directory named for the variant. BUG=b:265955979 BRANCH=None TEST=emerge-skyrim coreboot and boot up on Whiterun Change-Id: I3539f84e79c05936fe006bfe9d08743d6a9a6ba7 Signed-off-by: Isaac Lee <isaaclee@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72483 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-12 20:09:32 +0000