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path: root/src/northbridge/intel/haswell/northbridge.c
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* cpu/intel: Replace bsp_init_and_start_aps()Kyösti Mälkki2019-08-151-6/+1
* {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem()Subrata Banik2019-03-211-13/+1
* src: Use 'include <string.h>' when appropriateElyes HAOUAS2019-03-201-1/+1
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-041-1/+0
* device: Use pcidev_path_on_root()Kyösti Mälkki2019-01-061-1/+1
* device: Use pcidev_on_root()Kyösti Mälkki2019-01-061-1/+1
* nb/intel/haswell: Handle boards that do not support IGDTristan Corrick2018-12-291-7/+9
* nb/intel/haswell: Use DEVEN to disable devicesTristan Corrick2018-12-291-0/+46
* nb/intel/haswell: Add server processor host bridge device IDIru Cai2018-12-181-0/+1
* src: Remove unneeded include <cbmem.h>Elyes HAOUAS2018-11-161-1/+0
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-121-1/+0
* nb/intel/haswell: Consolidate memory controller PCI driver structsTristan Corrick2018-11-021-14/+9
* sb/intel/lynxpoint: Automatically generate the ACPI PCI routing tableTristan Corrick2018-11-011-0/+17
* nb/intel/haswell: Add a PCI ID for a desktop memory controllerTristan Corrick2018-11-011-0/+6
* northbridge: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS2018-09-251-2/+2
* northbridge/intel: Remove unneeded includesElyes HAOUAS2018-06-041-1/+0
* nb/intel/haswell: Get rid of device_tElyes HAOUAS2018-05-181-14/+18
* {mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber2018-05-081-1/+0
* nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APICMatt DeVillier2018-03-081-3/+16
* nb/intel/haswell: Generate ACPI DMAR tableMatt DeVillier2018-03-081-0/+1
* northbridge/intel/haswell: Fix undefined behaviorRyan Salsamendi2017-07-031-3/+9
* nb/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-06-271-1/+1
* nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>Arthur Heymans2017-01-061-1/+0
* src/northbridge: Improve code formattingElyes HAOUAS2016-09-121-13/+11
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-1/+1
* ACPI: Get S3 resume state from romstage_handoffKyösti Mälkki2015-03-101-22/+0
* northbridge/intel: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan2014-11-011-7/+3
* acpi: Remove explicit pointer tracking in per-device ssdt.Vladimir Serbinenko2014-10-111-1/+1
* haswell: Move to per-device ACPIVladimir Serbinenko2014-09-221-0/+1
* haswell: backup the default SMM region on resumeAaron Durbin2014-02-161-18/+2
* CBMEM intel: Define get_top_of_ram() once per chipsetKyösti Mälkki2014-01-151-10/+0
* haswell: Export functions for CPU family+model and steppingDuncan Laurie2013-12-121-14/+0
* haswell: Misc power management setup and fixesDuncan Laurie2013-12-071-80/+8
* CBMEM: Define cbmem_top() just once for x86Kyösti Mälkki2013-10-151-2/+2
* Fix MMCONF_SUPPORT_DEFAULT for ramstageKyösti Mälkki2013-07-101-5/+1
* haswell: fix overflow handling TOUUDAaron Durbin2013-06-031-2/+4
* boot: remove cbmem_post_handling()Aaron Durbin2013-05-011-5/+0
* resources: introduce reserved_ram_resource()Aaron Durbin2013-03-231-11/+10
* haswell: use dynamic cbmemAaron Durbin2013-03-221-0/+10
* coreboot: dynamic cbmem requirementAaron Durbin2013-03-221-15/+0
* haswell: use s3_resume field in romstage_handoffAaron Durbin2013-03-211-12/+13
* haswell: cbmem_get_table_location() implementationAaron Durbin2013-03-211-4/+15
* haswell: fix ACPI MCFG tableAaron Durbin2013-03-181-2/+2
* haswell: enable caching before SMM initializationAaron Durbin2013-03-181-10/+1
* haswell: include TSEG region in cacheable memoryAaron Durbin2013-03-171-2/+24
* haswell: don't add a 0-sized memory range resourceAaron Durbin2013-03-161-1/+2
* haswell: Fix BDSM and BGSM indicies in memory mapAaron Durbin2013-03-151-2/+2
* haswell: reserve default SMRAM spaceAaron Durbin2013-03-151-7/+33
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