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* arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki2018-06-061-1/+0
* cpu/intel/haswell: Switch to POSTCAR_STAGEArthur Heymans2018-06-052-0/+4
* src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS2018-06-041-1/+1
* northbridge/intel: Remove unneeded includesElyes HAOUAS2018-06-041-1/+0
* src/northbridge: Add and update license headersMartin Roth2018-05-291-0/+13
* nb/intel/haswell: Get rid of device_tElyes HAOUAS2018-05-185-22/+27
* {mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber2018-05-081-1/+0
* pci: Move inline PCI functions to pci_ops.hPatrick Rudolph2018-04-201-0/+1
* nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APICMatt DeVillier2018-03-083-3/+62
* nb/intel/haswell: Generate ACPI DMAR tableMatt DeVillier2018-03-083-0/+66
* nb/intel/haswell: Use the common MRC cache driverArthur Heymans2018-02-063-28/+13
* nb/intel/*.h: Remove left-over register definitionsPatrick Rudolph2018-01-311-2/+0
* 3rdparty/lib{hwbase,gfxinit}: Update to latest masterNico Huber2017-10-281-9/+1
* drivers/intel/gma: Put gma_gfxinit() into its own headerNico Huber2017-10-281-0/+1
* security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese2017-10-221-1/+1
* drivers/intel/gma/opregion: migrate from nb/commonMatt DeVillier2017-08-112-3/+2
* Rename __attribute__((packed)) --> __packedStefan Reinauer2017-07-132-4/+7
* nb/intel/haswell/gma: Set ASLS on S3 resumePatrick Rudolph2017-07-121-16/+17
* drv/intel/gma/opregion: Add interface for GNVS ASLB handlingPatrick Rudolph2017-07-121-1/+14
* northbridge/intel/haswell: Fix undefined behaviorRyan Salsamendi2017-07-063-7/+11
* northbridge/intel/haswell: Fix copy paste errorRyan Salsamendi2017-07-031-1/+1
* northbridge/intel/haswell: Fix undefined behaviorRyan Salsamendi2017-07-032-5/+11
* nb/haswell: set ASLB gnvs to OpRegion ACPI memory addressMatt DeVillier2017-06-291-0/+12
* nb/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-06-273-3/+3
* nb/intel/haswell/raminit: Die if cbmem_add() failsNico Huber2017-06-221-0/+2
* haswell: add CBMEM_MEMINFO table when initing RAMMatt DeVillier2017-06-162-0/+56
* nb/intel/haswell/gma: Use common init_igd_opregion methodPatrick Rudolph2017-06-154-130/+19
* nb/intel/haswell/gma: Write ACPI tablesPatrick Rudolph2017-06-151-0/+17
* device/Kconfig: Put gfx init methods into a `choice`Nico Huber2017-06-081-1/+1
* nb/intel/haswell: Fix up C NGI remnantsNico Huber2017-05-222-2/+1
* northbridge/haswell: clean up native graphics init codeMatt DeVillier2017-04-241-36/+19
* nb/intel: Deduplicate vbt headerPatrick Rudolph2017-04-033-169/+2
* vboot: Select SoC-specific configuration for all Chrome OS boardsJulius Werner2017-03-281-0/+3
* Only show CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM option when implementedArthur Heymans2017-02-041-0/+2
* nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>Arthur Heymans2017-01-061-1/+0
* nb/intel/haswell: Hook up libgfxinitArthur Heymans2016-12-201-2/+8
* MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki2016-12-071-1/+0
* PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki2016-12-071-2/+2
* Remove explicit select MMCONF_SUPPORTKyösti Mälkki2016-11-221-1/+0
* nb/intel: Fix some spelling mistakes in comments and stringsMartin Roth2016-11-212-2/+2
* src/northbridge: Remove unnecessary whitespaceElyes HAOUAS2016-10-041-1/+1
* northbridge/intel/haswell: Add space around operatorsElyes HAOUAS2016-09-203-4/+4
* src/northbridge: Improve code formattingElyes HAOUAS2016-09-121-13/+11
* northbridge/intel: Add required space before opening parenthesis '('Elyes HAOUAS2016-08-311-1/+1
* src/northbridge: Capitalize CPU, RAM and ROMElyes HAOUAS2016-07-311-1/+1
* bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh2016-07-282-3/+3
* nb/intel: Factor out common MRC codePatrick Rudolph2016-06-121-23/+1
* northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens2016-03-114-251/+1
* northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens2016-03-113-12/+3
* northbridge/intel: add missing #include guardsIru Cai2016-02-282-0/+10
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