coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	nb/intel/sandybridge: Use SPDX headers	Angel Pons	2020-03-25	1	-13/+2
*	nb/intel/sandybridge: Use cached CPUID	Angel Pons	2020-03-23	1	-1/+1
*	nb/intel/sandybridge: Store CPUID in ctrl struct	Angel Pons	2020-03-23	1	-2/+4
*	nb/intel/sandybridge: Add warning to saved structs	Angel Pons	2020-03-23	1	-0/+8
*	nb/intel/sandybridge: Remove unnecessary declaration	Angel Pons	2020-03-23	1	-2/+0
*	nb/intel/sandybridge: Tidy up code and comments	Angel Pons	2020-03-18	1	-35/+31
*	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi	2020-03-17	1	-3/+0
*	nb/intel/sandybridge/raminit_common.h: add missing stdint.h include	Felix Held	2020-01-27	1	-0/+2
*	nb/intel/sandybridge: replace NORTHBRIDGE with HOST_BRIDGE define	Felix Held	2020-01-27	1	-2/+3
*	nb/intel/sandybridge: Add a bunch of MCHBAR defines	Angel Pons	2020-01-10	1	-26/+29
*	nb/intel/sandybridge: replace .val_4028 with .io_latency	Felix Held	2020-01-01	1	-2/+2
*	nb/intel/sandybridge: move MCHBAR register definitions to sandybridge.h	Felix Held	2020-01-01	1	-4/+0
*	intel/sandybridge: Don't hardcode platform type	Patrick Rudolph	2018-07-28	1	-1/+0
*	nb/intel/sandybridge/raminit: Fix PDWN_mode on desktops	Patrick Rudolph	2018-07-26	1	-2/+3
*	nb/intel/sandybridge: support more XMP timings	Dan Elkouby	2018-04-16	1	-0/+2
*	nb/intel/sandybridge/raminit: Use Ivy Bridge specific values	Patrick Rudolph	2017-04-04	1	-0/+3
*	nb/intel/sandybridge/raminit: Separate Sandybridge and Ivybridge	Patrick Rudolph	2016-12-16	1	-1/+7
*	nb/intel/sandybridge/raminit: Split raminit.c	Patrick Rudolph	2016-12-05	1	-0/+180