coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	nb/intel/sandybridge: Factor out timing tables	Angel Pons	2020-03-25	1	-120/+37
*	nb/intel/sandybridge: Use SPDX headers	Angel Pons	2020-03-25	1	-13/+2
*	nb/intel/sandybridge: Use cached CPUID	Angel Pons	2020-03-23	1	-1/+1
*	nb/intel/sandybridge: Tidy up code and comments	Angel Pons	2020-03-18	1	-238/+179
*	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi	2020-03-17	1	-3/+0
*	nb/intel/sandybridge: Add a bunch of MCHBAR defines	Angel Pons	2020-01-10	1	-27/+27
*	nb/intel/sandybridge: Make MCHBAR arithmetics consistent	Angel Pons	2020-01-09	1	-2/+2
*	arch/io.h: Drop unnecessary include	Kyösti Mälkki	2019-03-04	1	-1/+0
*	src: Remove unneeded whitespace	Elyes HAOUAS	2018-10-23	1	-1/+1
*	northbridge/intel: Remove unneeded includes	Elyes HAOUAS	2018-06-04	1	-1/+0
*	nb/intel/sandybridge: support more XMP timings	Dan Elkouby	2018-04-16	1	-1/+4
*	nb/intel/ivybridge: Improve CAS freq selection	Arthur Heymans	2017-06-12	1	-99/+101
*	nb/intel/sandybridge/raminit: Add default values	Patrick Rudolph	2017-04-04	1	-3/+48
*	nb/intel/sandybridge/raminit: Add 100MHz refclock support	Patrick Rudolph	2017-04-04	1	-3/+40
*	nb/intel/sandybridge/raminit: Use Ivy Bridge specific values	Patrick Rudolph	2017-04-04	1	-93/+248
*	nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings	Arthur Heymans	2017-03-27	1	-10/+10
*	nb/intel/sandybridge/raminit: Separate Sandybridge and Ivybridge	Patrick Rudolph	2016-12-16	1	-0/+514