index
:
coreboot.git
24.02_branch
4.1
4.10_branch
4.11_branch
4.12_branch
4.14_branch
4.15_branch
4.16_branch
4.18_branch
4.19_branch
4.2
4.20_branch
4.22_branch
4.3
4.4
4.8_branch
classic-2014.10
coreboot-v1
coreboot-v3
main
master
rampayload
Coreboot firmware sources
coreboot
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path:
root
/
src
/
northbridge
/
intel
/
x4x
/
raminit_tables.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
nb/intel/x4x: Clean up cosmetics of raminit tables
Angel Pons
2021-02-07
1
-177
/
+200
*
nb/intel/x4x: Place raminit definitions in raminit.h
Angel Pons
2020-10-14
1
-1
/
+1
*
src/northbridge: Drop unneeded empty lines
Elyes HAOUAS
2020-09-21
1
-1
/
+0
*
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-05-11
1
-1
/
+0
*
treewide: replace GPLv2 long form headers with SPDX header
Patrick Georgi
2020-05-06
1
-12
/
+1
*
treewide: Move "is part of the coreboot project" line in its own comment
Patrick Georgi
2020-05-06
1
-2
/
+1
*
src (minus soc and mainboard): Remove copyright notices
Patrick Georgi
2020-03-17
1
-1
/
+0
*
arch/io.h: Drop unnecessary include
Kyösti Mälkki
2019-03-04
1
-1
/
+0
*
src: Fix typo
Elyes HAOUAS
2018-08-10
1
-1
/
+1
*
nb/intel/x4x: Adapt post JEDEC for DDR3
Arthur Heymans
2018-05-24
1
-0
/
+17
*
nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings
Arthur Heymans
2018-05-24
1
-0
/
+81
*
nb/intel/x4x: Add DDR3 JEDEC init
Arthur Heymans
2018-05-24
1
-0
/
+19
*
nb/intel/x4x: Add a convenient macro to loop over bytelanes
Arthur Heymans
2018-04-17
1
-10
/
+10
*
nb/intel/x4x: Refactor setting default dll settings
Arthur Heymans
2018-04-17
1
-0
/
+271