summaryrefslogtreecommitdiffstats
path: root/src/northbridge/intel/x4x
Commit message (Expand)AuthorAgeFilesLines
* arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki2018-06-061-1/+0
* nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans2018-06-053-7/+11
* nb/intel: Use postcar_frame_add_romcache()Nico Huber2018-06-041-2/+1
* northbridge/intel: Remove unneeded includesElyes HAOUAS2018-06-041-2/+0
* {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber2018-05-311-1/+1
* nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans2018-05-243-4/+33
* nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans2018-05-243-27/+136
* nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans2018-05-241-0/+8
* nb/intel/x4x: Implement write levelingArthur Heymans2018-05-243-2/+417
* nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans2018-05-244-7/+115
* nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans2018-05-141-5/+37
* nb/intel/x4x: Add DDR3 rcompArthur Heymans2018-05-141-31/+94
* nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans2018-05-141-56/+168
* nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans2018-05-141-37/+76
* nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans2018-05-142-9/+79
* nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans2018-05-141-6/+16
* nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans2018-05-144-40/+30
* nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans2018-05-142-27/+208
* nb/intel/x4x/raminit: Fix programming dual channel registersArthur Heymans2018-05-141-27/+59
* {mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber2018-05-081-1/+0
* nb/intel/x4x: Change memory layout to improve MTRRArthur Heymans2018-05-012-3/+16
* nb/intel/x4x: Fix programming CxDRBArthur Heymans2018-05-011-36/+9
* nb/intel/x4x: Implement both read and write trainingArthur Heymans2018-05-014-7/+522
* nb/x4x: Get rid of device_tElyes HAOUAS2018-04-304-11/+12
* nb/intel/x4x: Fix computing page_sizeArthur Heymans2018-04-281-2/+3
* nb/intel/x4x/rcven.c: Change the verbosity of some messagesArthur Heymans2018-04-171-8/+10
* nb/intel/x4x: Add a convenient macro to loop over bytelanesArthur Heymans2018-04-174-67/+69
* nb/intel/x4x: Clarify the raminit memory mappingArthur Heymans2018-04-173-30/+109
* nb/intel/x4x: Refactor setting default dll settingsArthur Heymans2018-04-174-94/+390
* nb/intel/x4x: Use SPI flash to cache raminit resultsArthur Heymans2018-04-176-94/+158
* device/ddr2,ddr3: Rename and move a few thingsArthur Heymans2018-02-221-1/+1
* nb/x4x/raminit_ddr2: Refactor clock configuration slightlyJonathan Neuschäfer2018-02-201-17/+14
* nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeoutArthur Heymans2018-01-051-0/+7
* nb/x4x/raminit: Rewrite SPD decode and timing selectionArthur Heymans2017-12-163-362/+271
* nb/intel/x4x/rcven.c: Fix programming coarse offsetArthur Heymans2017-12-121-2/+3
* nb/intel/*/gma: Port ACPI opregion to older platformsPatrick Rudolph2017-10-131-0/+56
* nb/intel/x4x: Select LAPIC_MONOTONIC_TIMERArthur Heymans2017-09-221-0/+1
* nb/intel/x4x: Fix booting with FSB800 DDR667 combinationArthur Heymans2017-08-201-1/+1
* nb/intel/x4x/raminit: Rework receive enable calibrationArthur Heymans2017-08-204-282/+378
* nb/intel/x4x/gma.c: Probe VGA EDID on DVI-I portsArthur Heymans2017-08-111-1/+14
* nb/intel/*/gma.c: Use macros for GMBUS numbersArthur Heymans2017-08-071-1/+1
* nb/intel/x4x: Rework programming DQ and DQS DLL timingsArthur Heymans2017-07-211-82/+51
* sb/intel/i82801jx: Add correct PCI ids and change namesArthur Heymans2017-07-213-1/+10
* Kconfig: Add choice of framebuffer modeNico Huber2017-06-041-4/+4
* Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFERNico Huber2017-06-021-0/+1
* Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFGNico Huber2017-06-021-0/+1
* nb/intel/x4x/raminit: Initialise async variableArthur Heymans2017-05-241-1/+1
* nb/intel/x4x: Use a struct for dll settings instead of an arrayArthur Heymans2017-05-222-104/+113
* nb/intel/x4x: Make raminit less verbose with CONFIG_DEBUG_RAM_SETUPArthur Heymans2017-05-212-3/+6
* nb/intel/x4x/raminit: Remove very long delayArthur Heymans2017-05-201-2/+0
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-11 01:45:24 +0000