| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ibe20d48bdd8c776f9658620a13814f96e564dabc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Generate IVRS for cezanne using common IVRS generation code.
BUG=b:190515051
TEST=Build cezanne coreboot image. Compare IVRS table with agesa
generated tables.
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ie15addba62ec7da25a7452512b6871e46c61b0a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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this adds the ALIB SSDT that gets passed from the FSP to coreboot via a
HOB.
BUG=b:185481298
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8a7dae5789eee442b321ddf276494eb53fc5f499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This function will be used to add some SSDTs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia88cb5ea483850a8659f3bae8040c82eb2735d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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