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path: root/src/soc/amd/cezanne/agesa_acpi.c
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* soc/amd: Fix some white spaces issuesElyes Haouas2022-07-171-1/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ibe20d48bdd8c776f9658620a13814f96e564dabc Reviewed-on: https://review.coreboot.org/c/coreboot/+/65907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/cezanne: Generate IVRS for cezanneJason Glenesk2021-08-051-0/+9
| | | | | | | | | | | | | | Generate IVRS for cezanne using common IVRS generation code. BUG=b:190515051 TEST=Build cezanne coreboot image. Compare IVRS table with agesa generated tables. Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: Ie15addba62ec7da25a7452512b6871e46c61b0a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/cezanne/agesa_acpi: add add_agesa_fsp_acpi_table callFelix Held2021-05-051-0/+4
| | | | | | | | | | | | | | this adds the ALIB SSDT that gets passed from the FSP to coreboot via a HOB. BUG=b:185481298 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8a7dae5789eee442b321ddf276494eb53fc5f499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/cezanne/agesa_acpi: add and call agesa_write_acpi_tablesFelix Held2021-05-051-0/+13
This function will be used to add some SSDTs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia88cb5ea483850a8659f3bae8040c82eb2735d26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>