coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/amd/cezanne: Turn off gpp clock request for disabled devices	Robert Zieba	2022-03-23	1	-3/+97
*	soc/amd/cezanne/fch: disable 48MHz output in S0i3	Felix Held	2021-12-20	1	-0/+2
*	soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume	Raul E Rangel	2021-12-08	1	-1/+0
*	src/soc/amd/cezanne: enable clock gating	Julian Schroeder	2021-10-13	1	-0/+23
*	src/soc to src/superio: Fix spelling errors	Martin Roth	2021-10-05	1	-1/+1
*	soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h	Felix Held	2021-09-23	1	-1/+1
*	soc/amd/cezanne/fch: implement and use fch_clk_output_48Mhz	Felix Held	2021-08-30	1	-0/+9
*	soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settings	Felix Held	2021-05-19	1	-0/+45
*	soc/amd/cezanne: Force resets to be cold	Marshall Dawson	2021-05-10	1	-0/+6
*	soc/amd/cezanne: Populate PCI_INTR registers	Raul E Rangel	2021-05-09	1	-0/+6
*	soc/amd/cezanne/fch: process ACPI PM/GPE and GPIO events	Felix Held	2021-04-14	1	-0/+6
*	soc/amd/cezanne: Initialize I2C	Zheng Bao	2021-03-22	1	-0/+3
*	soc/amd/cezanne: Add PCI IRQ Router definitions	Raul E Rangel	2021-02-12	1	-0/+72
*	soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports	Felix Held	2021-02-10	1	-2/+21
*	soc/amd/cezanne/fch: add ACPI I/O port setup	Felix Held	2021-02-05	1	-0/+29
*	soc/amd/cezanne: add empty ramstage FCH support	Felix Held	2021-01-29	1	-0/+11