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path: root/src/soc/amd/cezanne
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* soc/amd/cezanne/fch: process ACPI PM/GPE and GPIO eventsFelix Held2021-04-141-0/+6
* soc/amd/cezanne: save chipset state to CBMEMMartin Roth2021-04-142-0/+5
* soc/amd/cezanne: Set Power state after power failureKarthikeyan Ramasubramanian2021-04-102-1/+4
* soc/amd/cezanne: Add GRXS and GTXS methodEric Lai2021-04-101-0/+1
* soc/amd: remove special GPIO_2 override soc_gpio_hookKyösti Mälkki2021-04-081-10/+0
* soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSPMatt Papageorge2021-04-072-0/+60
* vc/amd/fsp/cezanne: update UPD headersMatt Papageorge2021-04-072-2/+1
* soc/amd/cezanne: Add soc/msr.hRaul E Rangel2021-04-051-0/+24
* soc/amd: Make espi_clear_decodes privateRaul E Rangel2021-04-051-3/+1
* soc/amd: Make espi_configure_decodes privateRaul E Rangel2021-04-051-1/+0
* soc/amd/cezanne: Clear eSPI ranges before configuring eSPIMartin Roth2021-04-051-0/+1
* soc/amd/cezanne: Add support to perform early EC syncKarthikeyan Ramasubramanian2021-04-021-0/+4
* soc/amd/cezanne: Enable GENERIC_GPIO_LIBRaul E Rangel2021-04-011-0/+1
* soc/amd/cezanne: Add device tree support for I2CRaul E Rangel2021-04-011-0/+8
* soc/amd/cezanne: Comment the AOAC register accessKarthikeyan Ramasubramanian2021-03-301-6/+12
* soc/amd/cezanne: factor out UPD-M configuration from romstageFelix Held2021-03-293-17/+23
* soc/amd/cezanne,picasso: rename fsp_params.c to fsp_s_params.cFelix Held2021-03-292-1/+1
* soc/amd: add DISABLE_KEYBOARD_RESET_PIN optionFelix Held2021-03-292-0/+12
* soc/amd/cezanne: Implement PROVIDES_ROM_SHARINGRaul E Rangel2021-03-292-0/+12
* soc/amd: move PM_RST_CTRL1 register definition to common acpimmio headerFelix Held2021-03-291-3/+0
* soc/amd/*/gpio: include types.h instead of stdint.h to have size_tFelix Held2021-03-291-1/+1
* mb/google/guybrush: disable KBRSTENKangheui Won2021-03-241-0/+1
* soc/amd/cezanne: select HAVE_EM100_SUPPORTFelix Held2021-03-231-0/+1
* soc/amd/cezanne: Initialize I2CZheng Bao2021-03-223-0/+9
* soc/amd/cezanne: Get I2C specific code for cezanneZheng Bao2021-03-228-0/+172
* soc/amd/cezanne/pci_gpp: Add ACPI names for GPP bridgesRaul E Rangel2021-03-181-0/+45
* soc/amd/cezanne: Add i2c controllers to chipset.cbMathew King2021-03-151-0/+5
* soc/amd/cezanne/Kconfig: turn on GOPNikolai Vyssotski2021-03-141-0/+2
* soc/amd/cezanne/acpi/soc.asl: Include sleepstates.aslRaul E Rangel2021-03-131-0/+2
* soc/amd/cezanne/fsp_params.c: GOP: pass VBIOS pointer to FSPNikolai Vyssotski2021-03-131-1/+2
* soc/amd/cezanne: Move globalnvs.asl to the correct locationMathew King2021-03-131-2/+2
* soc/amd: GOP: add UPD for VBIOS bufferNikolai Vyssotski2021-03-121-0/+8
* soc/amd/cezanne: add XHCI SCI/GEVENT setupFelix Held2021-03-122-0/+53
* soc/amd/common/block/smu: rename mailbox register definesFelix Held2021-03-121-7/+4
* soc/amd: move warm reset flag function prototypes to common codeFelix Held2021-03-113-11/+1
* soc/amd/cezanne: Add USB ports to chipset.cbMathew King2021-03-102-2/+52
* mb/amd/majolica: Update to use proper APCBs built for MajolicaMatt Papageorge2021-03-101-1/+1
* soc/amd/cezanne: select common APOB NV cache codeFelix Held2021-03-102-0/+5
* soc/amd/cezanne/smihandler: add ELOG and SMMSTORE supportFelix Held2021-03-101-2/+36
* soc/amd/cezanne/Makefile: pass APOB NV parameters to amdfwtoolFelix Held2021-03-091-0/+9
* soc/amd/cezanne: Include gpio.c in smmMathew King2021-03-081-0/+1
* soc/amd/cezanne: Allow GPIO defines to be used in ASLMathew King2021-03-081-1/+3
* soc/amd/cezanne/chipset.cb: clean up and change some aliasesFelix Held2021-03-041-24/+24
* soc/amd/cezanne/smihandler: implement S3 entry SMI handlerFelix Held2021-03-041-1/+23
* soc/amd/cezanne: add SMU supportFelix Held2021-03-044-0/+45
* soc/amd/cezanne/chipset.cb: rename alias for SATA controllersFelix Held2021-03-031-2/+2
* soc/amd/cezanne: Disable legacy DMA IO portsRaul E Rangel2021-03-022-0/+5
* soc/amd/cezanne: Fill out pci devices in chipset.cbMathew King2021-03-021-9/+49
* soc/amd/cezanne: Add PSP whitelist debug unlock supportRaul E Rangel2021-03-013-0/+24
* soc/amd/cezanne/acpi: Generate MADT LAPIC NMI settingsRaul E Rangel2021-02-261-0/+8
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