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* soc/amd/common/block/i2c/i23c_pad_def.h: fix off by one in defineFelix Held2022-04-011-1/+1
| | | | | | | | | | | | | | I23C_PAD_CTRL_SLEW_N_SHIFT is 6 and not 7 which matches both with the PPR #57243 revision 1.53 and with I23C_PAD_CTRL_SLEW_N_MASK which covers both bits 6 and 7. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I622717bebaffe34b6df5e578b082dc10e2a98256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63216 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/Kconfig: Drop obsolete fixed ramstage symbolsArthur Heymans2022-04-011-1/+2
| | | | | | | | | | | | On x86 ramstage is always relocated at runtime in cbmem so there is no need to have this configurable in Kconfig. Change-Id: I01b2335d0b82bea8f885ee5ca9814351bbf2aa3c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63215 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/lpc: Add support to not clear port80 enableKarthikeyan Ramasubramanian2022-03-292-1/+12
| | | | | | | | | | | | | | | | | SMU locks up sometimes if the port80 enable bit is cleared in the ESPI Decode register. Add a config to choose between clearing the entire ESPI Decode Register vs retaining the port80 enable bit. BUG=None TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/pi: Use -Wno-pragma-packArthur Heymans2022-03-251-0/+3
| | | | | | | | | | | Agesa headers extensively use and override pragma pack which fails to compile with clang. Change-Id: Ib234be536388f41d63c2d26cac4c35881af25930 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/pi/amd_late_init.c: Fix implicit enum conversionArthur Heymans2022-03-251-2/+3
| | | | | | | | | | | This fixes building with clang. Change-Id: Ifda9be8996703b06fe9ee30ffb5f56a91629e065 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* soc/amd/noncar/memmap.c: Fix formatted printArthur Heymans2022-03-251-1/+1
| | | | | | | | | | Fixes building with clang. Change-Id: I7027f3681e18b8ca0d2f0c899412806082846463 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63050 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/dmi.c: Fix implicit enum typingArthur Heymans2022-03-251-2/+3
| | | | | | | | | | Clang complains about implicit enum typing so make it explicit. Change-Id: I20aba3bd3af8a7292e04d2496c3cba1ab6ba3019 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/psp_verstage: Write postcodes after ESPI initKarthikeyan Ramasubramanian2022-03-231-3/+8
| | | | | | | | | | | | | | | | | On boards where PSP uses ESPI to write postcodes, update the verstage to do it after ESPI initialization. BUG=b:224543620 TEST=Build and boot to OS in Nipperkin. Ensure that there are no attempts to write the post code from PSP verstage before ESPI initialization. Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mohan Viswanathan Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common: move FCH IOAPIC and HPET init from SMBUs to LPC deviceFelix Held2022-03-222-10/+11
| | | | | | | | | | | | | | | | | Despite the SMBus device being function 0 of the FCH PCI device, the MMIO resource of the FCH IOAPIC is on the LPC device which is function 3 of the same PCI device, so move the FCH IOAPIC initialization code to the LPC device. Since the HPET was enabled in the same function, also move it to the LPC device initialization. TEST=On Mandolin both IOAPICs are still correctly detected by Linux. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block: Add mainboard_handle_smiRaul E Rangel2022-03-162-0/+9
| | | | | | | | | | | | | | | | | The current SMM framework only allows the mainboard code to handle GPEs. i.e., Events 0 - 23. This change allows the mainboard code to handle any SMI events not handled by the SoC code. This will allow the mainboard code to handle `SMITYPE_ESPI_SMI`. BUG=b:222694093 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I81943e8cb31e998f29cc60b565d3ca0a8dfe9cb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmemRaul E Rangel2022-03-102-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that SMM can write to CBMEM we can simply replay the transfer buffer cbmem console to move it into the main cbmem console. replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols. Since the SMM rmodule get linked with a different linker script than bootblock/romstage it doesn't have access to these symbols. In order to pass these symbols into SMM, we parse the bootblock.map file and generate an early_ram.ld script. This script is then used when linking SMM. I replay the buffer in `smm_soc_early_init` because this call happens before `console_init()`. `console_init()` prints the SMM header and we want to append the verstage contents before printing the header to avoid confusion. BUG=b:221231786 TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when doing `cbmem -c`. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTERFelix Held2022-03-092-11/+11
| | | | | | | | | | | | | | | Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to clarify that this isn't the address the SPI flash gets mapped, but the address of the SPI controller MMIO region. This also aligns the register name with the PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* timestamps: Rename timestamps to make names more consistentJakub Czapiga2022-03-082-12/+12
| | | | | | | | | | | | | | | | | | This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* src: Make PCI ID define names shorterFelix Singer2022-03-078-41/+41
| | | | | | | | | | | | | | | | | | Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/amd/common/vboot: Verify location of CBMEMC transfer bufferRaul E Rangel2022-03-021-0/+9
| | | | | | | | | | | | | | | | Since we want to read the non-x86 CBMEMC from SMM we need to be stricter on where we read from. This change forces the verstage binary and x86 code to agree on the CBMEMC transfer buffer location and size. BUG=b:221231786 TEST=Boot guybrush and verify verstage transfer buffer still ends up in cbmem Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/common/vboot: Remove parameter to replay_transfer_buffer_cbmemcRaul E Rangel2022-03-022-2/+7
| | | | | | | | | | | | | | We don't need to force the caller to look up and cast the transfer region. We can do it in the function. BUG=b:221231786 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib46a673ef5a43deb56a6d522152085036a47ab66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/common/vboot: Split transfer buffer methods into separate fileRaul E Rangel2022-03-023-83/+90
| | | | | | | | | | | | | | | | I want to reuse the transfer buffer methods in SMM, so I need to add them into their own file. I renamed `setup_cbmem_console` to `replay_transfer_buffer_cbmemc` so it has a more descriptive name. I also fixed the comment on `verify_psp_transfer_buf`. BUG=b:221231786 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da Reviewed-on: https://review.coreboot.org/c/coreboot/+/62348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/common/psp_verstage: Save transfer buffer during S0i3 resumeRaul E Rangel2022-03-021-0/+5
| | | | | | | | | | | | | | | | We need to save the transfer buffer so we can transfer the cbmem console and timestamps into x86 DRAM. BUG=b:221231786 TEST=Boot guybrush and verify S0i3 resume works. Also dumped the transfer buffer from the OS and verified the console contents got transferred. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1d3b34c90e0e18609b0c6a0cdedab35aeefbd84b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/common/fsp/fsp_validate.c: print warning instead of errorJulian Schroeder2022-03-011-1/+1
| | | | | | | | | | | | | If an AMD FSP binary has no valid image revision information, print a warning instead of an error. Change-Id: Ie9c5a387b81205fe93382778090260e41e261776 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62349 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/psp_verstage: Add missing post codes on S0i3 resumeRaul E Rangel2022-02-261-0/+4
| | | | | | | | | | | | | | | | We print these out in the normal flow, so lets add them for S0i3 resume as well. BUG=b:221231786 TEST=Perform suspend/resume cycle on guybrush and verify we get the new POST codes. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/{common/psp_verstage,soc/picasso}: Remove workbuf shrinkingRaul E Rangel2022-02-262-51/+11
| | | | | | | | | | | | | | This feature was never used. Let's remove it to keep things simple. BUG=221231786 TEST=Boot test guybrush and morphius and verify transfer buffer is correctly passed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I93a284db919f82763dcd31cec76af4b773eb3f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* soc/amd/common/block/lpc/espi_util: use __fallthroughFelix Held2022-02-221-5/+5
| | | | | | | | | | | | | | Using __fallthrough instead of a comment about the fall-through being intentional should make clang stop complaining about intended fall- through statements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I940529be02e20c72f6e97b2cfa10f0dd8f7020b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* soc/amd/common/block/psp/Makefile: add fmap_config.h dependencyFelix Held2022-02-181-1/+5
| | | | | | | | | | | Compiling efs_fmap_check.c depends on fmap_config.h already being generated, so add this dependency. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85e0900574f928d1594f8d1831ba58f959b75d27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/apob/apob_cache: use APOB cache size from FMAPFelix Held2022-02-182-3/+7
| | | | | | | | | | | Also add the Makefile dependency on the fmap_config.h file to make sure that this file already exists when it's included. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I540ea2c14fd187845efd3c0c8c1e4b8f82c8cac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/i2c: Add support for shared TPM_I2C controllerJan Dabros2022-02-171-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | There are platforms equipped with AMD SoC where I2C3 controller connected to TPM device is shared between X86 and PSP. In order to handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends acquire and release requests to be accepted by PSP. An example of implementation within Linux kernel is available [1]. There is a need to introduce new ACPI_ID ("AMDI0019") so that dedicated driver on OS side can bind to it and handle this special setup. Since PSP takes care of I2C controller power management, we need to remove PowerResource object from DSDT. BUG=b:204508404 BRANCH=guybrush [1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: Iccfc09d8c580d7ab2acb69d26b9c293cf625fb34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61863 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/soc: Remove space before tabElyes Haouas2022-02-171-1/+1
| | | | | | | | | | | Spaces before tabs are not allowed. Change-Id: I0d2c55c2e0108e59facd92b2e2c0f6c418ef6db0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62055 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amd/common/block/gpio/gpio: don't use -1 as bitmask in gpio_or32Felix Held2022-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | The and-mask passed to the gpio_update32 call needs all 32 bits to be set to ones. When building as 32 bit binary the -1UL will result in the needed bit mask, but for a 64 bit build the constant would have 64 bits set to ones which then gets truncated to 32 bits causing a compiler error. Use 0xffffffff as bit mask instead which behaves correctly in both cases and also clarifies what this is doing. TEST=Timeless build for Chausie results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0b6a50bd914fdbb7a78885efb6c610715e2d26c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62053 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aamir Bohra <aamirbohra@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amd/common/block/spi/fch_spi_ctrl: use uintptr_t for addressesFelix Held2022-02-171-1/+1
| | | | | | | | | | | | | | | | This fixes a build failure when trying to build the code in 64 bit mode. TEST=Timeless build for Chausie results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If8fe7b626d9d72c0b8ed07ced93e46f795e36848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamirbohra@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/psp: add PSP commandJason Glenesk2022-02-163-0/+63
| | | | | | | | | | | | | | | | | | | | Add PSP command to send SPL fuse command if PSP indicates SPL fusing is required. Also add Kconfig option to enable sending message. BUG=b:180701885 TEST=On a platform that supports SPL fusing. Build an image with an SPL table indicating fusing is required, confirm that PSP indicates fusing required and coreboot sends the appropriate command. A message indicating PSP requested fusing will appear in the log: "PSP: Fuse SPL requested" Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
* soc/amd/common/acp: add acp_gen2Fred Reitberger2022-02-155-0/+70
| | | | | | | | | | | | The gen2 ACP register definitions and locations are different from previous models. Specific code is refactored into acp_gen1 and acp_gen2. Update ACP register locations and definitions for gen2. Change-Id: If665b93cddf22435512f1276fcfee2f497dc6ef5 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/include/ioapic: make IOAPIC IDs not depend on MAX_CPUSFelix Held2022-02-131-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the APIC bus isn't used since a long time and the IOAPIC and LAPIC talk to each other via the system bus, there is no longer the requirement that the IOAPIC IDs mustn't overlap with the LAPIC IDs that start at 0 and end at CONFIG_MAX_CPUS - 1. The current Intel code uses 2 as the IOAPIC ID while most of their CPUs have more than 2 logical cores resulting in the IOAPIC having the same ID as one of the LAPICs. All chipsets in soc/amd use the defines for FCH_IOAPIC_ID and GNB_IOAPIC_ID for initializing the IOAPIC register, writing both MADT and IVRS ACPI tables and there's no MPTable support for those SoCs that might also rely on those IDs being consistent. This patch changes the definitions for FCH_IOAPIC_ID and GNB_IOAPIC_ID from CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 to 0 and 1. This also makes sure that the IOAPIC IDs still fit in 4 bits despite Cezanne having a CONFIG_MAX_CPUS of 16 resulting in the IOAPIC IDs being larger than 4 bits with the old code. While the Cezanne FCH IOAPIC supports 8 bits of IOAPIC IDs, this is non-standard. TEST=AMD Mandolin and Google Liara still work. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Id3a356480bb8407e0347cb5cef691fde7edc8deb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* soc/amd/common: Scan bridge devices behind SoCs GPU ControllerKevin Chiu2022-02-121-0/+1
| | | | | | | | | | | | | | Scan devices behind SoCs GPU controller to expose more buses. BUG=b:204401306 BRANCH=guybrush TEST=emerge-guybrush coreboot Change-Id: Ib78e6570f101c71efaf9cc1843defcb05301cd30 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/acp: introduce acp_gen1Fred Reitberger2022-02-115-38/+57
| | | | | | | | | | | Refactor existing acp code into acp_gen1 variant as preparation for gen2 variant in sabrina. Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/fsp: check fsp image revisionJulian Schroeder2022-02-111-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | Check if FSP binary and coreboot FSP structures (fspmupd.h) match sufficiently. A change in minor number denotes less critical changes or additions to the FSP API that still allow for the boot process to proceed. A change of the AMD image revision major number will halt boot. The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD Picasso, Cezanne and Sabrina APUs. BUG=b:184650244 TEST=build, boot and check fsp image revision info. Example: FSP major = 1 FSP minor = 0 FSP revision = 5 FSP build = 0 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/block/lpc/espi_util: add decode range register helpersFelix Held2022-02-111-18/+48
| | | | | | | | | | | | | | Introduce and use functions to translate eSPI IO/MMIO decode range IDs into the corresponding register bits and the IO/MMIO range and size register IDs into register offsets. This is a preparation to support the additional eSPI decode ranges on Sabrina where not all enable bits and base/size registers for one type of decode ranges are consecutive. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id91fe32447a06b049e33dfdacc8edfa2ebb2df39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/include/espi: rename IO/MMIO base/size registersFelix Held2022-02-111-14/+14
| | | | | | | | | | This aligns the register names more with the PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e7dc8dfc0fa5e86b9d4425f2496be86e039b686 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTIONFred Reitberger2022-02-093-0/+18
| | | | | | | | | | | | | | | | | | On systems that use the first 128kByte of the SPI flash for the EC firmware, it is not possible to place the EFS/amdfw part at the lowest location in flash where the on-chip PSP firmware will look for the EFS, since this is at an offset of 128kByte into the flash which is where the cbfs master header resides when the main CBFS is placed right after the EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION option that allows putting the EFS in a separate FMAP section that can be located right after the EC firmware FMAP section. The EFS FMAP partition is checked to ensure it begins at the expected location. Change-Id: I5ed0f76c9c9c9c180ee5f1b96f88689d0979bb5e Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/psp_verstage: Add UART support to PSP consoleRaul E Rangel2022-02-081-1/+8
| | | | | | | | | | | | | | | | | | This will allow PSP verstage to write logs to the serial console. We are no longer dependent on using a serial enabled PSP boot loader. Ideally we would delete this psp printk and use the standard printk. Since picasso doesn't currently support mapping the UART though, I'll keep it for now. BUG=b:215599230 TEST=Boot guybrush and verify PSP logs are output on serial console Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibd77cc754fae5baccebe7adc5ae0790c79236d26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner2022-02-0722-62/+60
| | | | | | | | | | | | | | | | | | | | | | | | | Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* nb,soc/amd/*/iommu: fix comment about IOMMU MMIO resourceFelix Held2022-02-051-1/+1
| | | | | | | | | | | | | | | | This comment was added with the AMD family 15h Trinity IOMMU support in commit 88ebbeb7e2a914330c869147bacb190b4270532f and looks like a copy of the comment about the subtractive decode ranges in the LPC device. The IOMMU doesn't have any subtractively decoded I/O or MMIO ranges and this is also not what the code does. This resource is the MMIO region to configure the IOMMU instead, so fix the comment in all copies of the IOMMU support code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2e1e3a46b839b9e58b836932c1bc9b41b1b1dc02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/include/acpimmio: drop 16 and 32 bit PM2 access functionsFelix Held2022-02-051-20/+0
| | | | | | | | | | | | | The PM2 ACPIMMIO region should only be accessed with 8 bit accesses. Using 16 or 32 bit read accesses will return the data from the first byte for all 2 or 4 bytes and 16 or 32 bit write accesses will result in only the first byte being written which is both unexpected behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5ace50d3b81b5bf3ea3b10aa02f25c58a6ea99b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/acpimmio/print_reset_status: extend bit name tableFelix Held2022-02-051-1/+3
| | | | | | | | | | | | | | | Bit 23 in the PM_RST_STATUS register is called LtReset on Stoneyridge and ShutdownMsg on Picasso/Cezanne/Sabrina. Bit 30 is reserved on Stoneyridge and defined as SdpParityErr on the newer SoCs. Bit 31 is only defined for Sabrina. Since the default value of undefined bits is 0 it isn't a problem to have descriptions for reserved reset status bits on some SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/i2c/i23c_pad_ctr: add & use I23C pad configurationFelix Held2022-02-046-0/+133
| | | | | | | | | | | | | | | | | | I2C bus 0..2 on Sabrina uses a different pad type which supports 1.1V and 1.8V levels, but doesn't support 3.3V I2C levels. Compared to the existing I2C pad control registers the bit definitions are different, so add a separate function to configure those pads which however still has the same function signature and is compatible with same data structs used for the devicetree settings. PPR #57243 Rev 1.50 was used as a reference. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/*/i2c: factor out common I2C pad configurationFelix Held2022-02-035-0/+105
| | | | | | | | | | | | | | | The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* psp_verstage: report developer mode to PSPKangheui Won2022-02-012-0/+3
| | | | | | | | | | | | | | | | | | Add platform_report_mode function which report current developer mode status to the PSP. L1 widevine app in the PSP will use this information to select key box. BUG=b:211058864 TEST=build and boot guybrush TEST=build picasso chrome os boards Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* drivers/i2c/designware/dw_i2c: return enum cb_err from dw_i2c_initFelix Held2022-02-011-1/+1
| | | | | | | | | | | | Using enum cb_err as return type instead of int improves the readability of the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I55e6d93ca141b687871ceaa763bbbbe966c4b4a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* soc/amd/cezanne,picasso,sabrina: factor out get_threads_per_coreFelix Held2022-01-262-0/+8
| | | | | | | | | | | | | | This code is common to at least all Zen-based APUs (Picasso, Cezanne, Sabrina) and is also useful outside of the SoC-specific dynamic ACPI table generation code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie96d4429fb6ed9223efed9b3c754e04052d7ca7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-by: Eric Peers <epeers@google.com>
* soc/amd/common: Don't reserve VERSTAGE region when using PSP verstageRaul E Rangel2022-01-261-1/+1
| | | | | | | | | | | | | | | | The VERSTAGE region is only needed when running verstage in the x86. This change reduces the early ram size by 512 KiB when using PSP verstage. BUG=none TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I45ce421397807dbb1eb48aedd05209b91e89aa4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/block/include/psp_efs: update defines for sabrinaFelix Held2022-01-251-1/+1
| | | | | | | | | | | | | Document #55758 Rev. 1.13 says that family 17h models 30h-3Fh and later use the spi_readmode_f17_mod_30_3f struct element for SPI_MODE_FIELD and spi_fastspeed_f17_mod_30_3f for SPI_SPEED_FIELD, so also use this for The AMD Sabrina SoC which is family 17h models A0h-AFh. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I336f9ea4a0defdf34e1af4b6d568cfe46488f75e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/common: Make the function in cpu.c available in romstageZheng Bao2022-01-241-0/+1
| | | | | | | | Change-Id: I909f74853a37a783582471e05071bc3d07e3dcf8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-13 19:25:33 +0000