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After adding code to handle the case of missing the link/bus on the CPU
cluster device in mp_cpu_bus_init, there's no need to have the LAPIC
device in the devicetree any more.
TEST=Mandolin still boots successfully.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icfc4fb61b373129f3bf4f4de09c38076a8f66733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Since the default state of the MMIO UART devices in the chipset
devicetree is off, the mainboard devicetree entries that disable MMIO
UART devices are removed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I913a587802020ce4e182b48632cdde1104c2a6e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55545
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06102f4fcc3bf9de332c71a52c632241b95cde19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.
Despite missing in the PPR, device pci 18.7 exists on Picasso.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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