| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/amd/stoneyridge: Add I2C devicetree support. | Justin TerAvest | 2018-01-25 | 1 | -0/+7 |
| * | amd/stoneyridge: Fix SPD files and functions camel case | Marc Jones | 2017-11-20 | 1 | -1/+1 |
| * | soc/amd/stoneyridge: Add UMA settings to devicetree | Aaron Durbin | 2017-11-10 | 1 | -0/+16 |
| * | soc/amd/common: Add DRAM clear option to northbridge.c | Richard Spiegel | 2017-11-10 | 1 | -0/+4 |
| * | amd/stoneyridge: Clarify SPD structure in chip.h | Marshall Dawson | 2017-11-03 | 1 | -1/+5 |
| * | soc/amd/stoneyridge: clean up chip.h | Martin Roth | 2017-10-17 | 1 | -6/+0 |
| * | soc/amd: Standardize guards on header files | Martin Roth | 2017-08-28 | 1 | -3/+3 |
| * | soc/amd/stoneyridge: Fix most checkpatch errors | Marshall Dawson | 2017-06-27 | 1 | -2/+1 |
| * | soc/amd/stoneyridge: Add northbridge support | Marc Jones | 2017-06-26 | 1 | -1/+4 |
| * | soc: Add AMD Stoney Ridge southbridge code | Marc Jones | 2017-06-26 | 1 | -0/+33 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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