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path:
root
/
src
/
soc
/
intel
/
alderlake
/
Makefile.inc
Commit message (
Expand
)
Author
Age
Files
Lines
*
soc/intel/alderlake: Hook-up public Alder Lake microcode
Michał Żygowski
2022-07-08
1
-0
/
+18
*
soc/intel/alderlake: add GPIO definitions for PCH-S
Michał Kopeć
2022-06-22
1
-6
/
+14
*
soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-S
Michał Żygowski
2022-06-16
1
-1
/
+1
*
soc/intel/alderlake: Add support to update descriptor at runtime
Reka Norman
2022-04-07
1
-0
/
+1
*
soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig
Sridhar Siricilla
2022-04-07
1
-1
/
+0
*
soc/intel/common: Abstract the common TCSS functions
John
2022-04-06
1
-0
/
+1
*
soc/intel/alderlake: Factor out A0 stepping workaround
Angel Pons
2022-01-11
1
-0
/
+1
*
soc/intel/alderlake: Implement function to map physical port to EC port
MAULIK V VAGHELA
2021-12-13
1
-0
/
+1
*
soc/intel/alderlake: Define soc_get_pcie_rp_type
Tim Wawrzynczak
2021-12-13
1
-0
/
+1
*
soc/intel/cse: config to enable oem key manifest
Ravindra N
2021-12-10
1
-1
/
+1
*
soc/intel/alderlake: Fix build failure with enabled CSE stitching
Bernardo Perez Priego
2021-11-15
1
-17
/
+17
*
Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
Hsuan-ting Chen
2021-11-15
1
-0
/
+2
*
cpu/x86: Introduce and use `CPU_X86_LAPIC`
Felix Held
2021-10-26
1
-1
/
+0
*
cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCs
Felix Held
2021-10-25
1
-1
/
+0
*
soc/intel/alderlake: Enable support for CSE stitching
Furquan Shaikh
2021-10-19
1
-0
/
+23
*
Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
Hsuan-ting Chen
2021-10-15
1
-2
/
+0
*
vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main
Hsuan Ting Chen
2021-09-16
1
-0
/
+2
*
cpu/x86/tsc: Deduplicate Makefile logic
Angel Pons
2021-09-08
1
-1
/
+0
*
soc/intel/alderlake: Configure the SKU specific parameters for VR domains
V Sowmya
2021-08-12
1
-0
/
+1
*
cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y
Arthur Heymans
2021-05-18
1
-1
/
+0
*
soc/intel/alderlake: Add CrashLog implementation for Intel ADL
Francois Toguo
2021-05-06
1
-0
/
+1
*
soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoC
Sumeet R Pawnikar
2021-04-23
1
-0
/
+1
*
soc/intel/alderlake: Enable logging of wake sources for S0ix
Sugnan Prabhu S
2021-03-30
1
-0
/
+2
*
soc/intel: Factor out common smmrelocate.c
Angel Pons
2021-03-03
1
-1
/
+0
*
soc/intel: Drop `bootblock_cpu_init()` function
Angel Pons
2021-03-01
1
-1
/
+0
*
soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
Tim Wawrzynczak
2021-02-24
1
-0
/
+1
*
soc/intel/alderlake: Update PCH and CPU PCIe RP table
Eric Lai
2021-01-18
1
-0
/
+2
*
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage
Subrata Banik
2020-10-03
1
-0
/
+26
*
soc/intel/alderlake: Add GPIOs for Alder Lake SOC
Subrata Banik
2020-09-27
1
-0
/
+7
*
soc/intel/alderlake/romstage: Do initial SoC commit till romstage
Subrata Banik
2020-09-15
1
-0
/
+14
*
soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock
Subrata Banik
2020-09-05
1
-0
/
+8