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path: root/src/soc/intel/alderlake/include
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* soc/intel/alderlake: Factor out A0 stepping workaroundAngel Pons2022-01-111-0/+2
* soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_modeSubrata Banik2022-01-021-1/+1
* src: Drop duplicated includesElyes HAOUAS2022-01-011-2/+0
* soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0Tim Wawrzynczak2021-12-091-1/+1
* soc/intel/alderlake: Add support for ADL-N CPU TypeUsha P2021-12-061-0/+1
* soc/intel/alderlake: Add support for ADL-N PCHUsha P2021-12-031-0/+1
* soc/intel/alderlake: Add Kconfigs for all PCH typesAngel Pons2021-12-021-0/+5
* soc/intel/alderlake: set lock offset for gpio pad communitiesNick Vaccaro2021-10-261-0/+3
* soc/intel: Update api name for getting spi destination idWonkyu Kim2021-10-261-5/+0
* soc/intel/alderlake: Align board type as per FSP v2347_00Ronak Kanabar2021-09-101-1/+2
* soc/intel/alderlake: Set LpmStateEnableMask UPDTim Wawrzynczak2021-09-101-0/+3
* soc/intel/alderlake: Add get_adl_cpu_type functionTim Wawrzynczak2021-09-101-0/+9
* soc/intel/alderlake: Configure the SKU specific parameters for VR domainsV Sowmya2021-08-121-0/+71
* soc/intel/alderlake: Add support for I2C6 and I2C7Varshit B Pandya2021-07-201-0/+2
* soc/intel/alderlake: Add virtual GPIOs for community 1Maulik V Vaghela2021-07-151-222/+277
* soc/intel/alderlake: Add missing devices to pci_devs.hTim Wawrzynczak2021-07-121-0/+26
* soc/intel/alderlake: Correct Bus and Device of Touch Host ControllerVarshit B Pandya2021-07-051-4/+4
* soc/intel/common: Move PMC EPOC related code to Intel common codeLean Sheng Tan2021-06-301-24/+0
* soc/intel/alderlake: Enable support for common IRQ blockTim Wawrzynczak2021-06-292-61/+1
* soc/intel/alderlake: Update mainboard_memory_init_params() argumentSubrata Banik2021-06-241-1/+1
* soc/intel/{alderlake,tigerlake}: Fix typo in pmc.hWerner Zeh2021-06-171-1/+1
* soc/intel/alderlake: Add validity for TBT firmware authenticationJohn Zhao2021-05-261-0/+4
* soc/intel/alderlake: Fix SA_DEVFN_CPU_PCIE6_*Tim Wawrzynczak2021-05-251-2/+2
* soc/intel/alderlake: mb/intel/sm: Add tcss codeDeepti Deshatty2021-05-181-0/+12
* soc/intel/alderlake: Add known CPU Port IDs for GPIO communitiesDeepti Deshatty2021-05-141-0/+6
* soc/intel/alderlake: Add IOM PCR PIDDeepti Deshatty2021-05-141-0/+1
* soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetrainingMaulik V Vaghela2021-05-101-0/+6
* soc/intel/alderlake: Add CrashLog implementation for Intel ADLFrancois Toguo2021-05-062-0/+31
* soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIOMaulik V Vaghela2021-05-052-99/+213
* soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OCMaulik V Vaghela2021-04-161-0/+16
* soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.hSubrata Banik2021-03-271-0/+6
* soc/intel/alderlake: Correct GPE DWx assignment as per EDSSubrata Banik2021-03-272-25/+19
* soc/intel/alderlake: Add provision to override Rcomp settingsSubrata Banik2021-03-261-8/+14
* soc/intel/alderlake: Align RcompResistor definition as per MRCSubrata Banik2021-03-261-4/+3
* soc/intel/alderlake: Remove obsolete CNVi Bluetooth PCI deviceCliff Huang2021-03-151-2/+0
* soc/intel/alderlake: Add some helper macros for accessing TCSS DMA devicesTim Wawrzynczak2021-03-031-0/+2
* soc/intel: Drop `bootblock_cpu_init()` functionAngel Pons2021-03-011-1/+0
* soc/intel: Drop `romstage_pch_init()` functionAngel Pons2021-03-011-1/+0
* soc/intel: Factor out common smbus.hAngel Pons2021-03-011-30/+3
* soc/intel: Factor out common gpe.hAngel Pons2021-03-011-114/+1
* soc/intel/alderlake: Fix PCI IRQ tablesTim Wawrzynczak2021-02-171-9/+10
* soc/intel: Drop aliases on MMCONF_BASE_ADDRESSKyösti Mälkki2021-02-161-3/+0
* soc/intel/alderlake: Remove pch.h from SoC directorySubrata Banik2021-01-301-10/+0
* soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driverFurquan Shaikh2021-01-251-81/+77
* soc/intel/alderlake: Update PCH and CPU PCIe RP tableEric Lai2021-01-182-2/+17
* soc/intel/alderlake: Add SPI DMI Destination IDSubrata Banik2020-12-231-0/+6
* soc/intel/alderlake: Add lp5_ccc_config to the board memory configurationSridhar Siricilla2020-11-291-0/+8
* mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'Subrata Banik2020-10-291-0/+6
* {cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner2020-10-241-1/+0
* soc/intel: convert XTAL frequency constant to KconfigMichael Niewöhner2020-10-211-3/+0
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