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path:
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src
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intel
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alderlake
/
meminit.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
soc/intel/alderlake: Implement WA for DDR5 DIMM modules
Meera Ravindranath
2021-07-13
1
-0
/
+27
*
soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwards
Bora Guvendik
2021-05-16
1
-5
/
+6
*
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00
Ronak Kanabar
2021-05-16
1
-8
/
+8
*
soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining
Maulik V Vaghela
2021-05-10
1
-0
/
+6
*
soc/intel/alderlake: Add provision to override Rcomp settings
Subrata Banik
2021-03-26
1
-2
/
+12
*
soc/intel/alderlake: Align RcompResistor definition as per MRC
Subrata Banik
2021-03-26
1
-3
/
+2
*
soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver
Furquan Shaikh
2021-01-25
1
-155
/
+210
*
soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration
Sridhar Siricilla
2020-11-29
1
-0
/
+1
*
mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'
Subrata Banik
2020-10-29
1
-0
/
+1
*
soc/intel/alderlake/romstage: Do initial SoC commit till romstage
Subrata Banik
2020-09-15
1
-0
/
+183