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path: root/src/soc/intel/alderlake/romstage
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* soc/intel/alderlake/fsp_params.c: Set DdrSpeedControl UPDFranklin Lin2022-07-201-1/+3
* soc/intel/alderlake: Support PCIe hardware compliance test modeSridahr Siricilla2022-07-141-0/+4
* soc/intel/alderlake: Add check for CSE FW sync in romstageKrishna P Bhat D2022-07-061-1/+1
* soc/intel/alderlake: Drop debug interface selectionSubrata Banik2022-06-261-3/+0
* soc/intel/alderlake: add GPIO definitions for PCH-SMichał Kopeć2022-06-221-1/+1
* soc/intel/alderlake: Skip PCIe source clock assignment if incorrectCliff Huang2022-06-181-0/+4
* soc/intel/{alderlake, common}: Rename the pre_mem_ft structureSridhar Siricilla2022-06-171-1/+1
* soc/intel: Rename heci_init to cse_initSubrata Banik2022-06-041-1/+1
* soc/intel/alderlake: Hook up FSP hyper-threading setting to option APIFelix Singer2022-05-261-2/+2
* soc/intel/adl/chip.h: Rename max_dram_speed to include unitsScott Chao2022-04-271-2/+2
* soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUGSubrata Banik2022-04-111-7/+16
* soc/intel/alderlake: Enable debug driver for Alder Lake platformSridhar Siricilla2022-04-061-0/+4
* soc/intel/alderlake: Update CPU IDs with correct steppingsLean Sheng Tan2022-04-042-2/+2
* soc/intel/alderlake: Use coreboot native event handler for FSP-M/SSubrata Banik2022-03-281-0/+6
* soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA2022-03-151-10/+10
* soc/intel/alderlake: Inject CSE TS into CBMEM timestamp tableBora Guvendik2022-03-101-0/+4
* drivers/wifi,soc/intel/adl: Move CnviDdrRfim property to driversTim Wawrzynczak2022-03-091-1/+8
* timestamps: Rename timestamps to make names more consistentJakub Czapiga2022-03-081-2/+2
* mb, soc: change mainboard_memory_init_params prototypeZhuohao Lee2022-02-251-2/+2
* soc/intel/alderlake: Fix function pointer typeArthur Heymans2022-02-211-1/+1
* Revert "soc/intel/adl: Skip sending MBP HOB to save boot time"MAULIK V VAGHELA2022-02-151-3/+0
* treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner2022-02-071-3/+3
* soc/intel/alderlake: Check clkreq overlapKane Chen2022-01-071-1/+8
* soc/intel/alderlake: Add option to make MRC log silentSubrata Banik2022-01-031-0/+3
* soc/intel/alderlake: Add timestamp for cse_fw_syncSridhar Siricilla2021-12-231-1/+5
* soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.hTim Wawrzynczak2021-12-061-10/+5
* soc/intel/adl: Add override skip_cse_sub_part_update() for alderlakeKrishna Prasad Bhat2021-12-031-0/+6
* soc/intel/alderlake: Add the CnviDdrRfim configurationRonak Kanabar2021-12-031-0/+3
* soc/intel/alderlake: Trigger cse_fw_sync before DRAM InitSridhar Siricilla2021-11-291-10/+4
* soc/intel/alderlake: Hook up common code for thermal configurationSubrata Banik2021-11-201-0/+11
* soc/intel/alderlake: Disable VT-d for early siliconsMeera Ravindranath2021-11-151-0/+9
* soc/intel/adl: Skip sending MBP HOB to save boot timeMAULIK V VAGHELA2021-10-261-0/+3
* soc/intel/alderlake: add MaxDramSpeed configCasper Chang2021-09-241-0/+2
* soc/intel/alderlake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik2021-07-171-1/+0
* soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDsSubrata Banik2021-07-151-4/+2
* soc/intel/alderlake: Update mainboard_memory_init_params() argumentSubrata Banik2021-06-241-2/+2
* soc/intel/alderlake/romstage: Refactor soc_memory_init_params functionSubrata Banik2021-06-171-46/+126
* soc/intel/alderlake/romstage: Update display UPDs based on InternalGfxSubrata Banik2021-06-161-22/+35
* soc/intel/alderlake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-161-35/+13
* soc/intel/alderlake/romstage: Drop ineffective FSP-M UPD `ChHashMask`Subrata Banik2021-06-081-2/+0
* soc/intel/alderlake: Set SaIpuEnable UPD according to devicetreeTim Wawrzynczak2021-06-081-0/+4
* soc/intel/alderlake: Set Base Addresses for TBT DMA remapping enginesSridhar Siricilla2021-06-071-0/+19
* soc/intel/alderlake: Add CrashLog implementation for Intel ADLFrancois Toguo2021-05-061-0/+6
* soc/intel/alderlake: Fill FSPM UPDs for VT-d configurationMeera Ravindranath2021-05-031-3/+30
* soc/intel/alderlake: Add enum for HDA audio configurationSugnan Prabhu S2021-04-221-1/+1
* soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.hFurquan Shaikh2021-04-221-7/+10
* soc/intel/alderlake: Enable CSE Lite driver for ADL platform in romstageSridhar Siricilla2021-03-171-1/+10
* soc/intel: Drop `romstage_pch_init()` functionAngel Pons2021-03-013-13/+3
* soc/intel/alderlake: Refactor PCIE port configEric Lai2021-02-051-21/+61
* soc/intel/alderlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGDSubrata Banik2021-01-211-5/+6
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