| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster | Kane Chen | 2021-05-07 | 1 | -0/+8 |
| * | soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage | Subrata Banik | 2020-10-03 | 1 | -0/+40 |
 |
index : coreboot.git | |
| Coreboot firmware sources | coreboot |
| summaryrefslogtreecommitdiffstats |