| Commit message (Expand) | Author | Age | Files | Lines |
* | device/Kconfig: Declare MMCONF symbols' type once | Angel Pons | 2021-01-29 | 1 | -1/+0 |
* | arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits | Kyösti Mälkki | 2021-01-28 | 1 | -4/+0 |
* | soc/intel/alderlake: Generate LP4x SPD files using gen_spd.go | Amanda Huang | 2021-01-27 | 6 | -0/+179 |
* | soc/intel: Move c-state resource define | Marc Jones | 2021-01-26 | 1 | -9/+0 |
* | soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver | Furquan Shaikh | 2021-01-25 | 3 | -236/+301 |
* | soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroring | Michael Niewöhner | 2021-01-25 | 2 | -25/+2 |
* | ACPI: Add helpers for CBMEM_ID_POWER_STATE | Kyösti Mälkki | 2021-01-23 | 1 | -5/+3 |
* | ELOG: Add const qualifier for chipset_power_state | Kyösti Mälkki | 2021-01-23 | 1 | -2/+2 |
* | soc/intel/alderlake: Adding Kconfig for ADL_M PCH | Varshit Pandya | 2021-01-22 | 1 | -0/+8 |
* | soc/intel/alderlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGD | Subrata Banik | 2021-01-21 | 1 | -5/+6 |
* | soc/intel/*: drop broken LPC mmio code | Michael Niewöhner | 2021-01-20 | 1 | -15/+0 |
* | ACPI GNVS: Drop most dev_count_cpu() | Kyösti Mälkki | 2021-01-20 | 1 | -3/+0 |
* | soc/intel/alderlake: Update PCH and CPU PCIe RP table | Eric Lai | 2021-01-18 | 5 | -9/+55 |
* | soc/intel/common: Move L1_substates_control to pcie_rp.h | Eric Lai | 2021-01-18 | 1 | -6/+2 |
* | soc/intel: rename uart_max_index | Michael Niewöhner | 2021-01-12 | 1 | -1/+1 |
* | soc/intel/alderlake: Add PCH ID 0x5182 | Subrata Banik | 2021-01-12 | 1 | -0/+1 |
* | soc/intel/uart: Drop SoC callback `soc_uart_console_to_device` | Furquan Shaikh | 2021-01-11 | 1 | -21/+5 |
* | soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs | Subrata Banik | 2021-01-10 | 4 | -14/+28 |
* | soc/intel: Rename to soc_fill_gnvs() | Kyösti Mälkki | 2021-01-10 | 1 | -1/+1 |
* | ACPI: Drop redundant ChromeOS setup for GNVS | Kyösti Mälkki | 2021-01-10 | 1 | -11/+0 |
* | ACPI: Drop redundant CONSOLE_CBMEM setup in GNVS | Kyösti Mälkki | 2021-01-10 | 1 | -4/+0 |
* | soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range() | Furquan Shaikh | 2021-01-08 | 1 | -2/+2 |
* | soc/intel/alderlake: Update CPU microcode patch base address/size | Subrata Banik | 2021-01-06 | 1 | -0/+11 |
* | soc/intel/common: Move gfx.asl to drivers/intel/gma | Matt DeVillier | 2020-12-30 | 1 | -1/+1 |
* | soc/intel: hook up new gpio device in the soc chips | Michael Niewöhner | 2020-12-30 | 2 | -0/+4 |
* | soc/intel/alderlake: Update chipset.cb for TCSS and USB | Eric Lai | 2020-12-29 | 2 | -6/+96 |
* | soc/intel/alderlake: Enable support for extended BIOS window | Subrata Banik | 2020-12-23 | 1 | -0/+7 |
* | soc/intel/alderlake: Add SPI DMI Destination ID | Subrata Banik | 2020-12-23 | 2 | -0/+13 |
* | soc/intel/alderlake: Drop unreferenced devicetree settings | Angel Pons | 2020-12-14 | 1 | -8/+0 |
* | soc/intel/common/dmi: Move DMI defines into DMI driver header | Srinidhi N Kaushik | 2020-12-09 | 1 | -3/+1 |
* | soc/intel/alderlake: Align chipset.cb with pci_devs.h | Eric Lai | 2020-12-04 | 1 | -8/+9 |
* | src/soc/intel/alderlake: Enable the PCH HDA | V Sowmya | 2020-12-04 | 1 | -0/+3 |
* | soc/intel/alderlake: Add initial chipset.cb | Tim Wawrzynczak | 2020-11-30 | 2 | -0/+71 |
* | soc/intel: Configure P2SB before other PCH controllers | Furquan Shaikh | 2020-11-29 | 1 | -2/+7 |
* | soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration | Sridhar Siricilla | 2020-11-29 | 2 | -0/+9 |
* | soc/intel/alderlake: Update UART0 GPIO as per latest schematics | Subrata Banik | 2020-11-23 | 1 | -2/+2 |
* | soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE | Subrata Banik | 2020-11-23 | 1 | -3/+3 |
* | soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and ... | Bora Guvendik | 2020-11-22 | 1 | -1/+1 |
* | soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD | Michael Niewöhner | 2020-11-20 | 1 | -2/+2 |
* | soc/intel/alderlake: Add PCH ID 0x5181 | Subrata Banik | 2020-11-12 | 1 | -0/+1 |
* | mb/intel: Enable ALC711 Audio codec over SNDW0 link | Sridhar Siricilla | 2020-11-07 | 1 | -2/+1 |
* | soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order | Subrata Banik | 2020-11-03 | 1 | -1/+1 |
* | soc/intel: Use of common reset code block | Subrata Banik | 2020-11-02 | 2 | -17/+2 |
* | mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg' | Subrata Banik | 2020-10-29 | 2 | -0/+7 |
* | soc/intel: deduplicate ACPI timer emulation | Michael Niewöhner | 2020-10-28 | 1 | -21/+0 |
* | mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` | Michael Niewöhner | 2020-10-26 | 1 | -2/+0 |
* | soc/intel: drop unneeded ISST configuration code | Michael Niewöhner | 2020-10-26 | 1 | -28/+0 |
* | soc/intel/alderlake/romstage: Skip GPIO configuration from FSP | Subrata Banik | 2020-10-25 | 1 | -0/+3 |
* | {cpu,soc}/intel: deduplicate cpu code | Michael Niewöhner | 2020-10-24 | 2 | -41/+1 |
* | soc/intel: convert XTAL frequency constant to Kconfig | Michael Niewöhner | 2020-10-21 | 3 | -8/+10 |