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path: root/src/soc/intel/baytrail/pcie.c
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* baytrail: fix the coding error on PCIe L1 exit latencyKevin L Lee2015-04-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The original code uses L1EXIT_MASK to shift the bit for PCIe L1 exit latency, the code should use L1EXIT_SHIFT for bit shifting. BUG=chrome-os-partner:34037 BRANCH=None TEST=build and boot on candy, verify B0:D28:F0 + 4Ch [17:15] set to 010b. Correspond WIFI device performance got improvement. Signed-off-by: Kevin L Lee <kevin.l.lee@intel.com> Change-Id: I3ac5b6319b726aa16cdb9678face89022d979517 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 381827e3d92c9e786cd8ebe412586968662fb4be Original-Change-Id: I8171f80720830cfa76f26778ae31c7590a723b92 Original-Reviewed-on: https://chromium-review.googlesource.com/234673 Original-Reviewed-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9480 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 msKevin Hsieh2015-04-101-1/+14
| | | | | | | | | | | | | | | | | | | Using REG_PCI_POLL32 to check if the LINK is active with 50ms timeout. BRANCH=none BUG=chromium:431169 TEST=Test on Enguarde, compile ok and boot OS Change-Id: If98ab4e31d17ec4e62d68b93edcec6d9aee87367 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: cf692ae9aebb43ab46cb07d36b62b300b16be1dc Original-Change-Id: I490e6ffa40979628edf52a7444808b6d25a6e83d Original-Signed-off-by: Kevin Hsieh <kevin.hsieh@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231777 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9478 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* baytrail: Change all SoC headers to <soc/headername.h> systemJulius Werner2015-04-071-4/+4
| | | | | | | | | | | | | | | | | | | This patch aligns baytrail to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Rambi. Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083 Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222026 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9363 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
* Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.Kenji Chen2015-04-041-0/+1
| | | | | | | | | | | | | | | | | | | BRANCH=master BUG=chrome-os-partner:33113 TEST=Build a image and test on Rambi. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I37add87e6fd3e7ad4eee09b8e0b312a2a89c7948 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 59b4c94be46b4397de7cb32726da9fa216e75a4c Original-Change-Id: I22c8f9730cc0e1ecc991f2dd7f2a1e7c548a1789 Original-Reviewed-on: https://chromium-review.googlesource.com/226654 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9272 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Baytrail: Change PCIe root disable algorithmKenji Chen2015-04-021-2/+37
| | | | | | | | | | | | | | | | | | | | | | | | | Disable Root Port0 only when there is no PCIe device present on any root port. BUG=None TEST=Boot Rambi with PCIe installed/non-installed on RP0 to confirm the RP0 is correctly enabled/disabled. However, I still need someone to help check if RP0(no device) is still enabled if there is device on other RPs since since I have no devices having slots from RP1/2/3. Change-Id: Iae552975250ed6f309c423b847621b8994172891 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c5cef0b7c2c146f0d46ed49b75fd2ec8369210ce Original-Change-Id: I7147569e78b2d1ecea070bc933773cdcae59f9e7 Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217791 Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9219 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* intel/baytrail: Spelling fixesMartin Roth2014-12-081-1/+1
| | | | | | | | Change-Id: Ideb58634a029d55746421ad1ea4b80811bca403c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7705 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* baytrail/rambi: S3 support and other updatesKein Yuan2014-10-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | baytrail: Change all GPIO related pull resistors from 10K to 20K Reviewed-on: https://chromium-review.googlesource.com/187570 (cherry picked from commit 762e99861dd1ae61ddcf1ebdec8e698ede54405e) baytrail: workaround kernel using serial console on resume Reviewed-on: https://chromium-review.googlesource.com/188011 (cherry picked from commit b0da3bdb5b6b417ad6cab0084359d4eae1cb4469) baytrail: allow dirty cache line evictions for SMRAM to stick Reviewed-on: https://chromium-review.googlesource.com/188015 (cherry picked from commit 50fb1e6a844e1db05574c92625da23777ad7a0ca) baytrail: Optionally pull up TDO and TMS to avoid power loss in S3. Reviewed-on: https://chromium-review.googlesource.com/188260 (cherry picked from commit e240856609b4eed5ed44ec4e021ed385965768d6) rambi: always load option rom Reviewed-on: https://chromium-review.googlesource.com/188721 (cherry picked from commit d8a1d108548d20755f8683497c215e76d513b7a9) baytrail: use new chromeos ram oops API Reviewed-on: https://chromium-review.googlesource.com/186394 (cherry picked from commit f38e6969df9b5453b10d49be60b5d033d38b4594) rambi: always show dev/rec screens on eDP connected panel Reviewed-on: https://chromium-review.googlesource.com/188731 (cherry picked from commit 7d8570ac52f68492a2250fa536d55f7cbbd9ef95) baytrail: stop e820 reserving default SMM region Reviewed-on: https://chromium-review.googlesource.com/189084 (cherry picked from commit 6fce823512f5db5a09a9c89048334c3524c69a24) baytrai: update MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/189196 (cherry picked from commit 36b33a25b6603b6a74990b00d981226440b68970) rambi: Put LPE device into ACPI mode Reviewed-on: https://chromium-review.googlesource.com/189371 (cherry picked from commit 5955350cd57fd1b3732b6db62911d824712a5413) baytrail: DPTF: Enable mainboard-specific PPCC Reviewed-on: https://chromium-review.googlesource.com/189576 (cherry picked from commit 27fae3e670244b529b7c0241742fc2b55d52c612) baytrail: Add config option for PCIe wake Reviewed-on: https://chromium-review.googlesource.com/189994 (cherry picked from commit 1cc31a7c021ec84311f1d4e89dd3e57ca8801ab5) rambi: Enable PCIe wake Reviewed-on: https://chromium-review.googlesource.com/189995 (cherry picked from commit c98ae1fee54cfb2b3d3c21a19cdbbf56a0bfa1e6) Squashed 13 commits for baytrail/rambi. Change-Id: I153ef5a43e2bede05cfd624f53e24a0013fd8fb4 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6957 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* baytrail: utilize reg_script_run_on_dev()Aaron Durbin2014-05-101-9/+2
| | | | | | | | | | | | | | | | | | | | | | The inclusion of reg_script_run_on_dev() allows for removing some of the chained reg_scripts just to set up the device context. Use the new reg_script function in those cases. BUG=None BRANCH=None TEST=Built and booted. Didn't see any bizarre dmesg or coreboot console output. Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438 Signed-off-by: Aaron Durbin <adurbin@chromium.og> Reviewed-on: https://chromium-review.googlesource.com/179541 Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5009 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* baytrail: pcie: Root port initializationAaron Durbin2014-05-071-0/+230
Add PCIe driver to initialize root ports. BUG=chrome-os-partner:24111 TEST=Manual on Rambi. Verify that PCIe Wifi card is detected and able to detect networks. BRANCH=None. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I3c68da5f27cd162e112add488bdf5ced192b7d12 Reviewed-on: https://chromium-review.googlesource.com/177652 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4981 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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