| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | baytrail: fix the coding error on PCIe L1 exit latency | Kevin L Lee | 2015-04-10 | 1 | -1/+1 |
| * | Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 ms | Kevin Hsieh | 2015-04-10 | 1 | -1/+14 |
| * | baytrail: Change all SoC headers to <soc/headername.h> system | Julius Werner | 2015-04-07 | 1 | -4/+4 |
| * | Baytrail: Fix no_dev_behind_port not executed for RP1/2/3. | Kenji Chen | 2015-04-04 | 1 | -0/+1 |
| * | Baytrail: Change PCIe root disable algorithm | Kenji Chen | 2015-04-02 | 1 | -2/+37 |
| * | intel/baytrail: Spelling fixes | Martin Roth | 2014-12-08 | 1 | -1/+1 |
| * | baytrail/rambi: S3 support and other updates | Kein Yuan | 2014-10-22 | 1 | -0/+6 |
| * | baytrail: utilize reg_script_run_on_dev() | Aaron Durbin | 2014-05-10 | 1 | -9/+2 |
| * | baytrail: pcie: Root port initialization | Aaron Durbin | 2014-05-07 | 1 | -0/+230 |
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| Coreboot firmware sources | coreboot |
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