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* broadwell: Fixes for _SWS supportDuncan Laurie2015-04-153-23/+23
* broadwell: Remove unused bootblock codeDuncan Laurie2015-04-151-15/+0
* broadwell: Clean up ME device and add new ME10 flowDuncan Laurie2015-04-154-148/+215
* soc/baytrail: Use microcode from the blobs repositoryMarc Jones2015-04-153-16322/+1
* soc/broadwell: Use microcode from the blobs repositoryMarc Jones2015-04-156-4254/+1
* broadwell: Remove TPM device from lpc.aslDuncan Laurie2015-04-143-26/+3
* broadwell: Work around VBIOS framebuffer issueDuncan Laurie2015-04-131-0/+9
* broadwell: Fix incorrect SATA port map maskWenkai Du2015-04-131-3/+3
* broadwell: Enable double self refresh by defaultDuncan Laurie2015-04-131-0/+1
* baytrail: correct NC pin to GPO pin according to BYT platform design guideKane Chen2015-04-101-1/+1
* broadwell: Correct XHCI offset for USB 3.0 portsJulius Werner2015-04-101-1/+1
* broadwell: Set PCIe replay timeout to 0xDDuncan Laurie2015-04-101-1/+1
* baytrail: add code for supporting 2x ddr refresh rateKane Chen2015-04-102-0/+14
* broadwell: Add configuration for tuning VR for C-state operationsDuncan Laurie2015-04-102-4/+38
* broadwell: Preserve VbNv around cmos_initDuncan Laurie2015-04-101-0/+27
* broadwell: Add function to apply PRR to a range of SPI flashDuncan Laurie2015-04-103-0/+50
* broadwell: Turn off panel backlight in S5 SMI handlerDuncan Laurie2015-04-101-0/+43
* broadwell: Skip steps when disabling PCIe portDuncan Laurie2015-04-101-2/+2
* broadwell: Remove XHCI workarounds on WPTDuncan Laurie2015-04-101-22/+46
* broadwell: Only do pre-graphics delay when running option romDuncan Laurie2015-04-101-0/+7
* broadwell: Fix PCIe ports programming sequences to enable HSIOPCWenkai Du2015-04-102-5/+33
* broadwell: Update SATA Gen3 TX adjustment registersDuncan Laurie2015-04-102-6/+18
* broadwell: Add a few bits to finalize stepDuncan Laurie2015-04-101-0/+3
* baytrail: fix the coding error on PCIe L1 exit latencyKevin L Lee2015-04-101-1/+1
* Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 msKevin Hsieh2015-04-101-1/+14
* Broadwell: Set boot_mode of pei_data before running reference codeKenji Chen2015-04-101-1/+4
* broadwell: Increase I2C SDA hold timing to 300nsChiranjeevi Rapolu2015-04-101-4/+4
* broadwell: add RCBA posting read after writingWenkai Du2015-04-101-15/+23
* Broadwell: Synchronization with FRC for Root Port Power ManagementKenji Chen2015-04-101-3/+10
* broadwell: Skip DDI-A enable in S3 resumeDuncan Laurie2015-04-101-1/+2
* broadwell: Add support for ACPI \_GPE._SWSDuncan Laurie2015-04-105-17/+57
* baytrail: Switch from ACPI mode to PCI mode for legacy supportMarc Jones2015-04-102-0/+60
* console: fix Kconfig usesPatrick Georgi2015-04-081-1/+1
* broadwell: Change all SoC headers to <soc/headername.h> systemJulius Werner2015-04-0783-223/+223
* baytrail: Change all SoC headers to <soc/headername.h> systemJulius Werner2015-04-0766-160/+160
* kconfig: drop intermittend forwarder filesStefan Reinauer2015-04-071-4/+0
* baytrail: Fix hdmi audio choppy issueKein Yuan2015-04-062-5/+13
* baytrail: reinitialize spi controller in SMM finalizationAaron Durbin2015-04-061-0/+21
* build system: rename __BOOT_BLOCK__ and __VER_STAGE__Patrick Georgi2015-04-041-4/+4
* broadwell: Enable turbo ratio if availableDuncan Laurie2015-04-041-4/+7
* Broadwell: Pass TSC value to romstage_mainLee Leahy2015-04-041-0/+6
* broadwell: fix typo in pei_dataDuncan Laurie2015-04-041-1/+1
* broadwell: Add USB3 PHY tuning fields to PEI DATADuncan Laurie2015-04-041-1/+14
* Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.Kenji Chen2015-04-041-0/+1
* Broadwell: Fix PCIe L1 Sub-State capability ID not filled.Kenji Chen2015-04-041-1/+4
* broadwell: Fix building with USE=quiet-cbDuncan Laurie2015-04-041-6/+6
* rmodule: use struct prog while loading rmodulesAaron Durbin2015-04-032-16/+24
* Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.Kenji Chen2015-04-022-0/+8
* broadwell: Disable ADSP power gating feature by defaultDuncan Laurie2015-04-022-13/+18
* broadwell: Add event log entry for GPIO27Duncan Laurie2015-04-021-0/+4
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