| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | FSP 1.1: Move common FSP code | Lee Leahy | 2015-10-27 | 1 | -1/+1 |
| * | cpu/mtrr.h: Fix macro names for MTRR registers | Alexandru Gagniuc | 2015-10-15 | 1 | -3/+3 |
| * | intel/braswell: allow dirty cache line evictions for SMRAM to stick | Chiranjeevi Rapolu | 2015-08-29 | 1 | -0/+10 |
| * | Braswell: Update to end of June. | Lee Leahy | 2015-07-06 | 1 | -1/+52 |
| * | Braswell: Add Braswell SOC support | Lee Leahy | 2015-06-25 | 1 | -73/+43 |
| * | Remove address from GPLv2 headers | Patrick Georgi | 2015-05-28 | 1 | -1/+1 |
| * | Braswell: Use Baytrail as Comparison Base | Lee Leahy | 2015-05-23 | 1 | -0/+309 |
 |
index : coreboot.git | |
| Coreboot firmware sources | coreboot |
| summaryrefslogtreecommitdiffstats |