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coreboot.git
24.02_branch
4.1
4.10_branch
4.11_branch
4.12_branch
4.14_branch
4.15_branch
4.16_branch
4.18_branch
4.19_branch
4.2
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4.22_branch
4.3
4.4
4.8_branch
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path:
root
/
src
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soc
/
intel
/
braswell
/
smihandler.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
cpu/x86: Separate save_state struct headers
Kyösti Mälkki
2019-08-13
1
-0
/
+1
*
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
Julius Werner
2019-03-08
1
-5
/
+5
*
device/mmio.h: Add include file for MMIO ops
Kyösti Mälkki
2019-03-04
1
-0
/
+1
*
device/pci: Fix PCI accessor headers
Kyösti Mälkki
2019-03-01
1
-0
/
+1
*
elog: make elog's SMM handler code follow everything else
Patrick Georgi
2018-12-05
1
-2
/
+2
*
src: Use of device_t is deprecated
Elyes HAOUAS
2018-06-14
1
-1
/
+1
*
soc/intel/braswell: use common Intel ACPI hardware definitions
Aaron Durbin
2016-07-15
1
-11
/
+11
*
soc/braswell: Fix leakage on V1P8S rail
Shobhit Srivastava
2016-01-27
1
-0
/
+2
*
Correct some common spelling mistakes
Martin Roth
2016-01-07
1
-1
/
+1
*
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-31
1
-4
/
+0
*
braswell: Tristate CFIO 139 and CFIO 140
Ravi Sarawadi
2015-09-08
1
-0
/
+6
*
Braswell: Add Braswell SOC support
Lee Leahy
2015-06-25
1
-119
/
+108
*
Remove address from GPLv2 headers
Patrick Georgi
2015-05-28
1
-1
/
+1
*
Braswell: Use Baytrail as Comparison Base
Lee Leahy
2015-05-23
1
-0
/
+483