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path: root/src/soc/intel/broadwell/romstage/romstage.c
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* soc/intel/broadwell: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* arch/x86: Remove <arch/cbfs.h>Kyösti Mälkki2019-12-271-1/+0
* src: Remove unused 'include <bootblock_common.h>'Elyes HAOUAS2019-12-181-1/+0
* drivers/elog: Add elog_boot_notify()Kyösti Mälkki2019-09-131-4/+2
* intel/broadwell: Use smm_subregion()Kyösti Mälkki2019-08-281-1/+0
* soc/intel: Use common romstage codeKyösti Mälkki2019-08-261-1/+0
* arch/x86: Add <arch/romstage.h>Kyösti Mälkki2019-08-221-1/+1
* cpu/intel: Enter romstage without BISTKyösti Mälkki2019-08-181-1/+1
* arch/x86: Add postcar_frame_common_mtrrs()Kyösti Mälkki2019-08-151-6/+0
* cpu/intel: Refactor platform_enter_postcar()Kyösti Mälkki2019-08-151-12/+4
* arch/x86: Adjust size of postcar stackKyösti Mälkki2019-07-041-3/+2
* Clean up unused arch/early_variables.h headerArthur Heymans2019-05-291-1/+0
* soc/intel/broadwell: Enable LPC/SIO setup in bootblockArthur Heymans2019-05-151-9/+0
* soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-05-151-3/+1
* soc/intel/broadwell: Use the common cpu/intel/car romstage entryArthur Heymans2019-05-151-19/+4
* soc/intel/broadwell: Clean up the bootflowArthur Heymans2019-05-141-24/+21
* soc/intel/broadwell: Don't use a pointer for pei_dataArthur Heymans2019-05-141-3/+2
* soc/intel/broadwell: Move GPIO init to a common placeArthur Heymans2019-05-141-0/+4
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-041-1/+0
* postcar: Make more use of postcar_frame_add_romcache()Nico Huber2019-02-121-2/+1
* cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCKKyösti Mälkki2019-01-081-4/+10
* soc/intel: Drop romstage_after_car()Kyösti Mälkki2018-12-281-8/+0
* soc/intel/broadwell: Implement postcar stageArthur Heymans2018-12-051-1/+34
* src: Remove unneeded include <cbmem.h>Elyes HAOUAS2018-11-161-1/+0
* src: Remove unneeded include <cbfs.h>Elyes HAOUAS2018-11-161-1/+0
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-121-1/+0
* intel: Use CF9 reset (part 1)Patrick Rudolph2018-10-221-1/+0
* Move compiler.h to commonlibNico Huber2018-10-081-1/+0
* drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese2018-07-251-4/+0
* security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese2018-06-041-4/+3
* src: Fix a typo on "mtrr"Elyes HAOUAS2018-04-261-1/+1
* compiler.h: add __weak macroAaron Durbin2018-04-241-1/+2
* security/tpm: Change TPM naming for different layers.Philipp Deppenwiese2018-01-181-1/+1
* security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese2018-01-181-1/+1
* vboot: Remove get_sw_write_protect_state callbackJulius Werner2017-07-181-7/+0
* soc/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-07-131-2/+2
* chromeos / broadwell / jecht: Make save_chromeos_gpios() jecht-specificJulius Werner2017-03-281-5/+1
* soc/intel/broadwell: Fix other issues detected by checkpatchLee Leahy2017-03-171-1/+1
* soc/intel/broadwell: Fix {}, () and conditional issuesLee Leahy2017-03-171-2/+3
* soc/intel/broadwell: Fix spacing issues detected by checkpatchLee Leahy2017-03-171-2/+2
* romstage_handoff: remove code duplicationAaron Durbin2016-12-011-8/+1
* lib/prog_loaders: use common ramstage_cache_invalid()Aaron Durbin2016-10-311-8/+0
* soc/intel/broadwell: use common Intel ACPI hardware definitionsAaron Durbin2016-07-151-3/+3
* intel romstage: Use run_ramstage()Kyösti Mälkki2016-06-291-2/+2
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin2015-09-241-2/+0
* chromeos: vboot and chromeos dependency removal for sw write protect statePaul Kocialkowski2015-09-231-3/+1
* broadwell: fix typoPatrick Georgi2015-06-231-1/+1
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