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path: root/src/soc/intel/cannonlake/romstage
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* soc/intel: Rename heci_init to cse_initSubrata Banik2022-06-041-1/+1
* soc/intel/cannonlake: Hook up FSP hyper-threading setting to option APIFelix Singer2022-05-261-0/+3
* soc/intel/cnl: Enable CSE FW sync for CSE LITE SKUMatt DeVillier2022-02-151-1/+11
* soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-MMatt DeVillier2022-01-261-0/+1
* ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki2021-11-091-1/+0
* soc/intel/cannonlake: Merge soc_memory_init_params() into its callerFelix Singer2021-05-101-14/+5
* soc/intel/cannonlake/romstage: Reuse device pointerFelix Singer2021-04-201-3/+3
* soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPDAngel Pons2021-04-081-1/+3
* soc/intel: Drop `romstage_pch_init()` functionAngel Pons2021-03-013-13/+3
* {soc,vc,mb}/intel: Drop support for Cannon Lake SoCFelix Singer2021-01-111-2/+0
* soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()Nick Vaccaro2020-10-051-6/+0
* mb, soc: change mainboard_get_dram_part_num() prototypeNick Vaccaro2020-10-051-8/+16
* soc/intel: rename get_prmrr_sizeMichael Niewöhner2020-09-211-1/+1
* soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddressSridhar Siricilla2020-08-121-0/+3
* src: Update bare access to BOOL CONFIG_ vals to CONFIG()Martin Roth2020-07-261-1/+1
* soc/intel/cannonlake: Move tco_configure to bootblockTim Wawrzynczak2020-07-221-4/+0
* src: Remove leading blank lines from SPDX headerElyes HAOUAS2020-05-181-3/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-115-5/+0
* src/: Replace GPL boilerplate with SPDX headersPatrick Georgi2020-05-091-9/+1
* soc/intel/cannonlake: Add DisableHeciRetry to configChristian Walter2020-05-041-0/+4
* soc/intel/cannonlake: Steal no memory for disabled IGDChristian Walter2020-04-091-5/+22
* soc/intel/cannonlake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-064-52/+8
* soc: Remove copyright noticesPatrick Georgi2020-03-185-7/+0
* soc/intel/cannonlake: Add chip config for SATA strengthJamie Chen2020-01-181-0/+22
* soc/intel/cannonlake: Refactor pch_early_init() codeUsha P2019-12-263-0/+30
* soc/intel/cannonlake: Add chip config to override CPU flex ratioSubrata Banik2019-11-261-4/+8
* soc/intel/sgx: convert SGX and PRMRR devicetree options to KconfigMichael Niewöhner2019-11-041-1/+2
* soc/intel: Rename <intelblocks/chip.h>Kyösti Mälkki2019-09-291-1/+1
* soc/intel: Move fill_postcar_frame to memmap.cKyösti Mälkki2019-08-281-16/+0
* soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c codeSubrata Banik2019-08-271-0/+1
* intel/car: Use common TS_START_ROMSTAGEKyösti Mälkki2019-08-261-2/+0
* soc/intel: Use common romstage codeKyösti Mälkki2019-08-261-14/+6
* arch/x86: Add <arch/romstage.h>Kyösti Mälkki2019-08-221-0/+1
* soc/intel: Use config_of()Kyösti Mälkki2019-07-181-1/+1
* soc/intel: Replace uses of dev_find_slot()Kyösti Mälkki2019-07-041-4/+4
* arch/x86: Adjust size of postcar stackKyösti Mälkki2019-07-041-1/+2
* soc/intel: Provide SPD manufacturer ID and module type to SMBIOSDuncan Laurie2019-06-211-1/+3
* soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASEArthur Heymans2019-06-211-1/+1
* vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155Aamir Bohra2019-06-121-0/+4
* src/soc/intel/common/smbios: Add addtional infos to dimm_infoChristian Walter2019-06-061-1/+5
* soc/intel: Fill DIMM serial number from SPDDuncan Laurie2019-05-181-0/+1
* soc/intel/cnl: Enable VT-dJohn Zhao2019-05-111-0/+5
* soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS2019-04-262-2/+4
* soc/intel/cannonlake: Enable PlatformDebugConsent by KconfigKane Chen2019-04-231-2/+3
* src: include <assert.h> when appropriateElyes HAOUAS2019-04-231-1/+0
* Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"Lijian Zhao2019-04-221-4/+1
* soc/intel/cannonlake: Configure Vmx support using KconfigRonak Kanabar2019-04-161-5/+2
* soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CMLSubrata Banik2019-04-161-1/+4
* soc/intel/cannonlake: Update CPU Ratio base on MSRLijian Zhao2019-03-281-13/+6
* soc/intel/common: Remove common chip config use_fsp_mp_initSubrata Banik2019-03-241-1/+2
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