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path: root/src/soc/intel/cannonlake
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* soc/intel/cannonlake: Set MAX_CPUS based on the SoC and PCHFelix Singer2022-07-231-1/+4
* treewide: Remove unused <cpu/x86/mtrr.h>Elyes Haouas2022-07-201-1/+0
* soc/intel/common/pch: Decouple CLIENT from BASEAngel Pons2022-07-201-1/+1
* soc/intel/cannonlake: Update VR config for Coffee LakeChristian Walter2022-07-151-36/+65
* soc/cannonlake: Hook up Comet Lake U 06-a6-01 microcodeMichał Żygowski2022-06-221-1/+1
* device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki2022-06-221-1/+1
* soc/intel/cannonlake/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-092-9/+9
* soc/intel/cannonlake/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-092-2/+2
* soc/intel/cannonlake/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-093-11/+11
* soc/intel/cannonlake/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-092-12/+12
* soc/intel: Rename heci_init to cse_initSubrata Banik2022-06-041-1/+1
* soc/intel/common/cpu: Use SoC overrides to set CPU privilege levelSubrata Banik2022-06-021-0/+9
* soc/intel/cannonlake: Hook up FSP hyper-threading setting to option APIFelix Singer2022-05-262-0/+4
* soc/intel/*: Use SSDT to pass A4GB and A4GSArthur Heymans2022-05-162-3/+2
* soc/inte/*/gpio; Add GPE_EN and GPE_STS register definitionMaulik V Vaghela2022-05-162-0/+12
* soc/{amd/stoneyridge,intel}: Don't select VBOOT_SEPARATE_VERSTAGEArthur Heymans2022-04-291-1/+0
* soc/intel: Decouple HECI disabling interface from HECI disable KconfigSubrata Banik2022-04-291-3/+3
* soc/intel/cmn/lockdown: Perform SA lockdown configurationSubrata Banik2022-04-271-8/+0
* soc/intel: Remove unused <cbmem.h>Elyes HAOUAS2022-04-221-1/+0
* soc/intel/cannonlake: Drop unused LPC BIOS Control macroSubrata Banik2022-04-211-4/+0
* soc/intel: clean up dmi driver codeWonkyu Kim2022-04-201-6/+0
* soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODESridhar Siricilla2022-04-061-0/+1
* soc/intel: Move `pmc_clear_pmcon_sts()` into IA common codeSubrata Banik2022-03-293-17/+1
* src: Make PCI ID define names shorterFelix Singer2022-03-072-267/+267
* intelblocks/pcie: Correct mapping between LCAP port and coreboot indexMAULIK V VAGHELA2022-02-251-5/+5
* arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held2022-02-251-2/+0
* drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik2022-02-181-0/+3
* soc/intel/cnl: Move selection of DISABLE_HECI1_AT_PRE_BOOT back to mainboardMatt DeVillier2022-02-151-3/+0
* soc/intel/cnl: switch to PMC/IPC for HECI disable on SOC_INTEL_COMETLAKEMatt DeVillier2022-02-153-3/+10
* soc/intel/*/pmc: Add `finalize` operation for pmcSubrata Banik2022-02-151-0/+17
* soc/intel/cnl: Enable CSE FW sync for CSE LITE SKUMatt DeVillier2022-02-151-1/+11
* treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner2022-02-072-2/+2
* cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki2022-02-051-3/+0
* soc/intel/cannonlake: Forbid FSP from disabling HECI1Subrata Banik2022-02-031-3/+6
* soc/intel/cannonlake: Add `disable_vmx` devtree optionAngel Pons2022-02-022-1/+4
* soc/intel/cannonlake: Use SBI msg to disable HECI1Subrata Banik2022-02-022-1/+2
* soc/intel/common/cse: Rework heci_disable functionSubrata Banik2022-02-021-1/+1
* soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-MMatt DeVillier2022-01-261-0/+1
* soc/intel/common/cpu: Use SoC overrides to get CPU privilege levelSubrata Banik2022-01-192-0/+10
* soc/intel/cnl: Use Kconfig to disable HECI1Subrata Banik2022-01-173-5/+5
* soc/intel: Remove unused <string.h>Elyes HAOUAS2022-01-051-1/+0
* soc/intel/cannonlake/acpi: Replace Multiply(a,b) with ASL 2.0 syntaxFelix Singer2022-01-012-2/+2
* soc/intel/cannonlake/acpi: Replace Add(a,b) with ASL 2.0 syntaxFelix Singer2021-12-313-4/+3
* soc/intel/cannonlake/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer2021-12-312-2/+2
* soc/intel/cannonlake/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer2021-12-302-9/+9
* soc/intel/cannonlake/acpi: Replace LAnd() with ASL 2.0 syntaxFelix Singer2021-12-303-12/+10
* soc/intel/{skl,cnl}: Guard USB macro parametersAngel Pons2021-12-261-1/+1
* soc/intel/cannonlake: Configure common FSP memory settings only onceFelix Singer2021-12-131-2/+2
* soc/intel/cannonlake: Rename SA_DEV_SLOT_DSPFelix Singer2021-12-122-5/+5
* soc/intel/{skylake/cannonlake}: Fix bug in vr_configAngel Pons2021-12-101-1/+1
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