summaryrefslogtreecommitdiffstats
path: root/src/soc/intel/common/block/systemagent
Commit message (Expand)AuthorAgeFilesLines
* soc/intel: Add some missing MCH PCIe IDsKeno Fischer2019-06-071-0/+3
* soc/intel/skylake: Add PCI Id for Kabylake DTChristian Walter2019-05-231-0/+1
* Change the guard for bootblock_systemagent_early_init to ENV_BOOTBLOCKRonald G. Minnich2019-05-091-1/+1
* soc/intel/common: Inject SMBIOS type 16 tableLijian Zhao2019-04-191-0/+35
* src: Use include <delay.h> when appropriateElyes HAOUAS2019-04-061-1/+0
* src: Use #include <timer.h> when appropriateElyes HAOUAS2019-04-061-1/+1
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-3/+3
* soc/intel/skylake: Add new Northbridge and IGD IDsMaxim Polyakov2019-03-061-0/+1
* device/mmio.h: Add include file for MMIO opsKyösti Mälkki2019-03-041-1/+1
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-041-1/+0
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-012-0/+2
* soc/intel/cannonlake: Add Comet Lake U SA 2+2 Device IDSubrata Banik2019-02-281-0/+1
* soc/intel/common: Include cometlake SA IDsRonak Kanabar2019-02-241-0/+7
* intelblocks/systemagent: Add ACPI table generation hookWerner Zeh2019-01-281-0/+12
* soc/{amd,intel}: Remove needless '&' on function pointersElyes HAOUAS2019-01-231-3/+3
* soc/intel/common: Include Icelake device IDsAamir Bohra2018-11-071-0/+4
* soc/intel/cannonlake: Add new cannon lake PCH-H supportpraveen hodagatta pranesh2018-10-171-1/+3
* Move compiler.h to commonlibNico Huber2018-10-081-1/+0
* src: Use tabs for indentationElyes HAOUAS2018-10-081-2/+2
* soc/intel/common/block: Don't use device_t in ramstageElyes HAOUAS2018-09-181-2/+3
* soc/intel/common/block: Add WHL 2-core SKUKrzysztof Sywula2018-08-201-1/+2
* src/soc/intel: Add new device IDs to support coffeelakeMaulik2018-08-101-0/+1
* soc/intel/common/block: Add WhiskeyLake (WHL) IDsKrzysztof Sywula2018-08-011-0/+1
* soc/intel/skylake: Generate ACPI RMRR tableMatt DeVillier2018-06-301-1/+1
* compiler.h: add __weak macroAaron Durbin2018-04-241-4/+5
* soc/intel/common: Configure all possible GFX DSM memory reserve rangeSubrata Banik2018-04-111-1/+26
* soc/intel: Add KBL-S MCH and some KBL PCH supportGaggery Tsai2018-03-261-0/+1
* src/soc: Fix various typosJonathan Neuschäfer2018-02-201-3/+3
* soc/intel/skylake: Add Kabylake PCH H device ID'sV Sowmya2018-02-071-0/+1
* soc/intel/common/block: Add option to have subsystem_id in common pci driverSubrata Banik2017-12-131-0/+1
* soc/intel/common: Add function to get soc reserved memory sizeSubrata Banik2017-09-221-4/+14
* intel/common/systemagent: Add API to get SOC specific PRMRR base and maskPratik Prajapati2017-09-141-0/+7
* soc/intel/common: Add functions into common system agent librarySubrata Banik2017-08-301-1/+18
* soc/intel/common: Early system agent library access in postcar stageSubrata Banik2017-08-231-0/+1
* soc/intel/common: Add functions into common system agent librarySubrata Banik2017-08-233-21/+59
* soc/intel/common: Add Cannonlake pci ids for commonLijian Zhao2017-08-041-0/+2
* src/soc/intel: Don't allow user to select PCIe config mmio sizeArthur Heymans2017-06-161-3/+3
* src/soc/intel/common: Don't allow user to change PCIe BARArthur Heymans2017-06-161-1/+1
* soc/intel/common/block: Add Intel common systemagent supportSubrata Banik2017-06-095-32/+512
* soc/intel/common/block: Add Intel common systemagent supportSubrata Banik2017-03-283-0/+86
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-09 03:05:29 +0000