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path: root/src/soc/intel/denverton_ns/Kconfig
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* soc/intel: drop Kconfig `PM_ACPI_TIMER_OPTIONAL`Michael Niewöhner2021-11-081-1/+0
* arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki2021-10-221-1/+0
* soc/intel/{skl,cnl,dnv}: disable PM ACPI timer if chosenMichael Niewöhner2021-10-171-0/+1
* soc/intel/dnv_ns: enable uCode PM Timer emulationMichael Niewöhner2021-10-161-0/+1
* soc/intel/dnv_ns: add the Kconfig value for CPU_XTAL_HZMichael Niewöhner2021-10-091-0/+3
* soc/intel/denverton_ns: Sanity check MMCONF_BASE_ADDRESSKyösti Mälkki2021-08-191-0/+4
* src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons2021-07-021-1/+0
* src: Move `select ARCH_X86` to platformsAngel Pons2021-06-301-0/+1
* soc/intel/denverton_ns: Remove SOC specific FSP location overridesArthur Heymans2021-06-161-21/+2
* cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki2021-06-071-1/+0
* device/Kconfig: Declare MMCONF symbols' type onceAngel Pons2021-01-291-1/+0
* arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limitsKyösti Mälkki2021-01-281-4/+0
* soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config optionShreesh Chhabbi2020-12-141-1/+1
* src/soc/intel/denverton_ns: Use improvement in coreboot since 4.9Julien Viard de Galbert2020-11-201-3/+23
* {cpu,soc}/intel: replace AES-NI locking by common implemenation callMichael Niewöhner2020-10-211-0/+1
* drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen2020-10-021-1/+0
* arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons2020-09-261-4/+1
* soc/intel/common/cpu: Update COS mask calculation for NEM enhanced modeAamir Bohra2020-09-141-1/+1
* soc/intel/denverton_ns/Kconfig: Drop unused 'IQAT_MEMORY_REGION_SIZE'Elyes HAOUAS2020-09-081-7/+0
* cpu,soc/intel: Drop select SMPKyösti Mälkki2020-07-261-1/+0
* ACPI: Remove Kconfig COMMON_FADTKyösti Mälkki2020-06-101-1/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* {security,soc}/*/Kconfig: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS2020-05-081-13/+2
* fsp2_0: Gather Kconfig declarationsNico Huber2020-04-051-3/+0
* intel/fsp2_0: Make FSP_USE_REPO a SoC opt-inJohanna Schander2020-03-301-0/+1
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* soc/intel/denverton_ns: Allow including microcodeFelix Singer2020-03-041-0/+1
* soc/intel/denverton_ns: Allow using FSP repoFelix Singer2020-03-041-0/+9
* src: capitalize 'RAM'Elyes HAOUAS2020-02-241-1/+1
* soc/intel/common/systemagent: Add Kconfig guardAndrey Petrov2020-01-301-0/+4
* soc/intel/dnv: Remove commented out Kconfig optionSubrata Banik2020-01-061-1/+0
* soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-TSubrata Banik2019-11-261-8/+0
* Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans2019-11-251-1/+0
* drivers/intel/fsp2_0: move common cbmem_top_chipset to fsp driverMichael Niewöhner2019-11-111-1/+0
* soc/intel/denverton_ns: make use of common cbmem_top_chipsetMichael Niewöhner2019-11-111-0/+1
* cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki2019-11-031-1/+0
* arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki2019-08-111-1/+0
* arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki2019-08-111-1/+0
* cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki2019-07-091-1/+0
* soc/intel/denverton_ns: Enable ACPI using intelblockJulien Viard de Galbert2019-01-251-0/+2
* soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLEVanessa Eusebio2019-01-181-0/+1
* console: Change BOOTBLOCK_CONSOLE default to `y`Nico Huber2019-01-141-1/+0
* drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IONico Huber2018-11-201-1/+1
* soc/intel/.../Kconfig: Move GPIO debug option into debug menuNico Huber2018-11-181-1/+1
* soc/intel/denverton_ns/Kconfig: Remove unused HSUART_FUNCElyes HAOUAS2018-11-161-4/+0
* intel: Use CF9 reset (part 2)Patrick Rudolph2018-10-221-1/+0
* soc/intel/denverton_ns: Enable common block PMCJulien Viard de Galbert2018-09-141-0/+2
* src/*/intel/: clarify Kconfig options regarding IFDStefan Tauner2018-09-131-0/+1
* arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki2018-06-061-1/+0
* soc/intel/denverton_ns: Enable common code for CPUJulien Viard de Galbert2018-05-141-0/+5
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