coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel: implement ACPI timer disabling per SoC and drop common code	Michael Niewöhner	2021-10-17	1	-1/+1
*	soc/intel: move disabling of PM Timer to SoC PMC code	Michael Niewöhner	2021-10-17	1	-0/+9
*	soc/intel/{cnl,jsl,tgl,ehl,adl}: rename PMC device init/enable callbacks	Michael Niewöhner	2021-09-29	1	-4/+4
*	soc/intel/jasperlake: Switch to runtime generation of Intel Power Engine	Tim Wawrzynczak	2021-09-10	1	-0/+10
*	soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT	Kane Chen	2021-05-07	1	-0/+8
*	soc/intel: Move pmc_soc_set_afterg3_en() to pmutil.c	Angel Pons	2021-04-21	1	-17/+0
*	soc/intel/jasperlake: Run pmc_set_acpi_mode() during .init in pmc_ops	Kane Chen	2020-08-24	1	-2/+15
*	soc/intel/jasperlake: Add JSL PMC as 'hidden' PCI device	Tim Wawrzynczak	2020-06-07	1	-9/+19
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	soc/intel/jasperlake: Use SPDX for GPL-2.0-only files	Angel Pons	2020-04-06	1	-13/+2
*	soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake	Aamir Bohra	2020-03-28	1	-6/+0
*	soc/intel/jasperlake: Add Jasper Lake SoC support	Aamir Bohra	2020-03-28	1	-0/+113