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path: root/src/soc/intel/skylake/chip.c
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* src: change coreboot to lowercaseMartin Roth2017-06-071-1/+1
* soc/intel/skylake: Wrap lines at 80 columnsLee Leahy2017-03-171-5/+10
* soc/intel/skylake: Add int to unsignedLee Leahy2017-03-171-1/+2
* soc/intel/skylake: Fix broken suspend-resumeFurquan Shaikh2017-02-221-0/+5
* soc/intel/skylake: Perform CPU MP Init before FSP-S InitSubrata Banik2017-02-141-2/+2
* soc/intel/skylake: Add USB Port Over Current (OC) Pin programmingSubrata Banik2016-11-281-0/+3
* soc/intel/skylake: move i2c voltage config to own variableAaron Durbin2016-11-111-1/+1
* soc/intel/skylake: Add FSP 2.0 support in ramstageNaresh G Solanki2016-09-191-299/+5
* src/soc: Add required space before opening parenthesis '('Elyes HAOUAS2016-08-311-3/+3
* skylake: Move I2C bus configuration to separate structureDuncan Laurie2016-06-091-2/+3
* skylake: Add ACPI device name handlerDuncan Laurie2016-05-211-0/+69
* soc/intel/skylake: add option to enable VR specific mailbox cmdRizwan Qureshi2016-03-121-0/+4
* intel/skylake: Adding provision to set voltages to the I2C portsNaresh G Solanki2016-01-191-0/+20
* intel/skylake: Change in UPD name from SkipMpInit to FspSkipMpInitBarnali Sarkar2016-01-181-1/+1
* intel/skylake: provide default VR configurationAaron Durbin2016-01-181-22/+2
* intel/skylake: disable heci1 if psf is unlockedArchana Patni2016-01-171-0/+12
* intel/skylake: Add VrConfig UPD parameters from corebootRizwan Qureshi2016-01-161-1/+173
* intel/skylake: Enable SkipMpInit tokenRizwan Qureshi2016-01-161-0/+2
* intel/skylake: More UPD params are added for PCH policy in FSPRizwan Qureshi2016-01-151-3/+86
* intel/skylake: Update UPD parameters as per FSP 1.8.0Barnali Sarkar2016-01-151-0/+173
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* intel/skylake: Clean up USB configuration in devicetreeDuncan Laurie2015-10-271-20/+25
* FSP 1.1: Replace soc_ prefix with fsp_Lee Leahy2015-10-271-90/+90
* intel/skylake: IRQ programming through UPDSubrata Banik2015-10-271-0/+282
* intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params updateRizwan Qureshi2015-10-271-6/+24
* intel/skylake: Create "RtcLock" Silicon UPD from corebootBarnali Sarkar2015-09-171-0/+3
* fsp1_1: provide binding to UEFI versionAaron Durbin2015-09-101-1/+1
* skylake: Apply USB2 and USB3 port enable/disable settingsDuncan Laurie2015-09-081-11/+9
* skylake: only generate ACPI cpu entries onceAaron Durbin2015-08-271-0/+2
* skylake: Update Memory and Silicon Init paramsRizwan Qureshi2015-08-191-1/+175
* skylake: remove the redundant fspNotify in chip final.robbie zhang2015-07-291-9/+0
* soc/intel: Add Skylake SOC supportLee Leahy2015-07-161-14/+51
* soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy2015-07-161-0/+80
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