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path: root/src/soc/intel/tigerlake/acpi
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* soc/intel/tigerlake: Replace spaces with tabsSean Rhodes2022-06-221-5/+5
* soc/intel/tigerlake: Hide PMC and IOM devicesMichał Kopeć2022-03-071-0/+2
* soc/intel/tigerlake: Add config option for S3 ACPISean Rhodes2021-11-154-123/+180
* soc/intel/tigerlake/apci: Only use SCM for ChromeOSSean Rhodes2021-11-151-0/+7
* soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimizationJohn Zhao2021-10-111-0/+59
* src/soc to src/superio: Fix spelling errorsMartin Roth2021-10-051-1/+1
* soc/intel/tigerlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak2021-09-101-3/+0
* soc/intel/tigerlake: Add USB ACPI devices for PCH-HJeremy Soller2021-08-241-0/+36
* soc/intel/tigerlake: Add TGL-H PEG portsJeremy Soller2021-08-241-0/+22
* soc/intel/tigerlake: Add PCIe root ports for PCH-HJeremy Soller2021-08-241-4/+158
* soc/intel/tigerlake: Add PCH-H GPIO definitionsJeremy Soller2021-08-242-0/+151
* soc/intel/tigerlake: Enable support for common IRQ blockTim Wawrzynczak2021-06-292-162/+0
* soc/intel/tigerlake: Return TBT PowerResource from PR0 and PR3John Zhao2021-05-272-14/+20
* soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI deviceCliff Huang2021-03-151-1/+0
* soc/intel: Include gfx.asl from northbridgeAngel Pons2021-03-011-3/+0
* soc/intel/tigerlake: Remove polling for Link Active Status at resumeJohn Zhao2021-02-231-12/+0
* soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0John Zhao2021-02-041-2/+0
* soc/intel/common: Move gfx.asl to drivers/intel/gmaMatt DeVillier2020-12-301-1/+1
* soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPDMichael Niewöhner2020-11-201-2/+2
* soc/intel/tigerlake: Enable and use USB4 PCIe driverDuncan Laurie2020-10-142-106/+0
* soc/intel: Make use of common gfx.aslSubrata Banik2020-10-081-0/+3
* soc/intel/tigerlake: Update TCSS PM flowJohn Zhao2020-10-052-23/+29
* soc/intel/tigerlake/acpi: Convert 'pch_hda.asl' into ASL 2.0 syntaxSubrata Banik2020-10-051-1/+1
* soc/intel/common/block/acpi: Factor out common ish.aslSubrata Banik2020-10-052-10/+1
* soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik2020-10-051-20/+0
* soc/intel/common/block/acpi: Factor out common smbus.aslSubrata Banik2020-10-052-9/+1
* mb/{google,intel}/{volteer,tglrvp}: Refer to common IPU ASLSubrata Banik2020-10-051-10/+0
* soc/intel/common/block/acpi: Factor out common pch_glan.aslSubrata Banik2020-10-052-14/+3
* soc/intel/common/block/acpi: Factor out common gpio_op.aslSubrata Banik2020-09-272-127/+1
* soc/intel/{jsl,tgl}: Fix GRXS function to get GPIO number properSubrata Banik2020-09-271-1/+1
* soc/intel/{jsl,tgl}: Refactor gpio_op.aslSubrata Banik2020-09-251-6/+6
* src: Remove unneded whitespace before tabElyes HAOUAS2020-08-181-6/+6
* src: Remove extra lines in license headerElyes HAOUAS2020-07-264-16/+4
* soc/intel/tigerlake: Configure Type-C Input Output Manager(IOM) deviceJohn Zhao2020-07-121-0/+10
* soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4John Zhao2020-07-011-25/+41
* src: Remove whitespaces before tabsElyes HAOUAS2020-06-301-2/+2
* soc/intel/tigerlake: Fix unresolved symbol CDW1 errorJohn Zhao2020-06-241-2/+3
* soc/intel/tigerlake: Update platform.asl to ASL2.0 syntaxV Sowmya2020-06-221-1/+1
* soc/intel/tigerlake: Update TCSS for SW CM supportJohn Zhao2020-06-194-220/+219
* tigerlake: add unique acpi device ids for dptfSumeet R Pawnikar2020-06-191-0/+9
* soc/intel/tigerlake: Add Hot-Plug and PME event handlers for ThunderboltJohn Zhao2020-06-101-114/+237
* soc/intel/tigerlake/acpi: Update gpio_op.asl to ASL2.0 syntaxVenkata Krishna Nimmagadda2020-06-071-16/+15
* soc/intel/tigerlake/acpi: Update pch_hda.asl to ASL2.0 syntaxVenkata Krishna Nimmagadda2020-05-311-8/+6
* soc/intel/tigerlake/acpi: Update camera_clock_ctl.asl to ASL2.0Venkata Krishna Nimmagadda2020-05-311-2/+1
* soc/intel/tigerlake: Generate PMC ACPI device at runtimeTim Wawrzynczak2020-05-282-29/+0
* soc/intel/tigerlake: Correct GPIO community PID configurationEric Lai2020-05-281-5/+5
* soc/intel/tigerlake: Fix wrong operation region for CPU to PCH methodJohn Zhao2020-05-261-2/+2
* soc/intel/tigerlake: Fix wrong operation region for CPU to PCH methodJohn Zhao2020-05-182-4/+4
* soc/intel/tigerlake: Correct IRQ interruptWonkyu Kim2020-05-121-115/+121
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-1119-19/+0
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