coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel/tigerlake: Add Jasper lake GPIO support	Ronak Kanabar	2020-03-03	1	-4/+4
*	soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig	Subrata Banik	2020-03-01	1	-11/+0
*	soc/intel/tigerlake: Update FSP params for Jasper Lake	Maulik V Vaghela	2020-02-27	1	-0/+9
*	soc/intel/tigerlake: Enable Audio on TGL	Srinidhi N Kaushik	2020-02-17	1	-13/+11
*	soc/intel/tigerlake: Configure TCSS xHCI and xDCI	Wonkyu Kim	2020-02-01	1	-1/+5
*	soc/intel/tigerlake: Enable DP ports according to board design	Wonkyu Kim	2020-01-28	1	-0/+26
*	soc/intel/tigerlake: Update chip files	Ravi Sarawadi	2020-01-18	1	-56/+25
*	soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h	Furquan Shaikh	2019-12-12	1	-6/+0
*	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik	2019-11-09	1	-0/+280