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path: root/src/soc/intel/tigerlake/fsp_params.c
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* soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during bootBrandon Breitenstein2021-03-051-1/+1
* soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and socBrandon Breitenstein2021-03-051-3/+2
* soc/intel/tigerlake: Enable end of post support in FSPNick Vaccaro2021-02-221-0/+15
* soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard designShreesh Chhabbi2021-02-101-1/+53
* soc/intel/tgl: Add configurable value for UsbTcPortEnBrandon Breitenstein2021-01-141-0/+1
* soc/intel/tigerlake: Disable TC cold supportSrinidhi N Kaushik2021-01-131-0/+3
* soc/intel/tigerlake: Enable USB2 port reset message on Type-C portsJohn Zhao2021-01-081-0/+3
* soc/intel/tigerlake: Expose UPD to enable Precision Time MeasurementDuncan Laurie2020-11-201-0/+1
* soc/intel/tigerlake: Add code for early tcssBrandon Breitenstein2020-11-131-0/+6
* soc/intel/tigerlake: Disable C1 C-state DemotionRavi Sarawadi2020-11-051-0/+4
* soc/intel/tigerlake: Add Acoustic featuresShaunak Saha2020-10-231-0/+8
* soc/intel/tigerlake: Add support for CnviBtCore and CnviBtAudioOffloadJohn Zhao2020-09-241-0/+7
* soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widthsJamie Ryu2020-09-231-0/+17
* soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by defaultMichael Niewöhner2020-09-061-2/+10
* soc/intel/tigerlake: Add mainboard hook for overriding SoC configJes Klinke2020-09-021-0/+6
* soc/intel/tigerlake: Allow fine grained control of S0iX statesJes Klinke2020-08-171-0/+8
* soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecatedSubrata Banik2020-08-011-5/+1
* soc/intel/tigerlake: Configure TCSS D3Hot and D3ColdJohn Zhao2020-07-291-2/+8
* soc/intel/tigerlake: Simplify is-device-enabled checksFelix Singer2020-07-281-28/+8
* src: Update bare access to BOOL CONFIG_ vals to CONFIG()Martin Roth2020-07-261-3/+3
* soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2Subrata Banik2020-07-211-0/+20
* soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDsShaunak Saha2020-07-151-0/+24
* soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO bootJamie Ryu2020-07-031-1/+15
* tigerlake: enable tcc_offset functionalitySumeet R Pawnikar2020-06-301-0/+3
* soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPDWonkyu Kim2020-06-171-0/+1
* soc/intel/tigerlake: Add devicetree support to change PCH VR settingsVenkata Krishna Nimmagadda2020-06-121-0/+23
* soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMsJohn Zhao2020-06-091-0/+7
* soc/intel/tigerlake: Configure THCWonkyu Kim2020-05-281-0/+18
* soc/intel/tigerlake: Disable VMDWonkyu Kim2020-05-261-0/+7
* soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnableJohn Zhao2020-05-261-0/+4
* tigerlake: enable DPTF functionality for volteerSumeet R Pawnikar2020-05-201-0/+3
* soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfgBrandon Breitenstein2020-05-201-1/+1
* soc/intel/tigerlake: Control SATA and DMI power optimizationShaunak Saha2020-05-121-0/+9
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetreeMeera Ravindranath2020-05-011-0/+5
* soc/intel/tigerlake: Merge the recent change from other platformsWonkyu Kim2020-04-201-5/+13
* soc/intel/tigerlake: Implement CHIPSET_LOCKDOWNWonkyu Kim2020-04-141-0/+14
* soc/intel/tigerlake: Configure RP settingWonkyu Kim2020-04-141-2/+5
* soc/intel/tigerlake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc/intel/tigerlake: Remove Jasper Lake SoC referencesAamir Bohra2020-04-011-0/+213
* soc/intel/tigerlake: Select correct fsp_param as per SoC KconfigMaulik V Vaghela2020-01-131-46/+0
* soc/intel/tigerlake: Include soc common lpss header fileAamir Bohra2019-12-111-1/+1
* soc/intel/tigerlake: Do initial SoC commit till ramstageSubrata Banik2019-11-091-0/+46
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