coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	{mb, soc}: Move mrc_cache invalidating logic into `memory` common code	Subrata Banik	2022-03-15	1	-2/+1
*	soc/intel/common: Pass `FSPM_UPD *` argument for spd functions	Subrata Banik	2022-03-15	1	-2/+2
*	{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype	Subrata Banik	2022-03-15	1	-1/+2
*	mb, soc: Add the SPD_CACHE_ENABLE	Zhuohao Lee	2022-03-02	1	-1/+3
*	soc/intel/tigerlake: Hook up FSP repository	Felix Singer	2021-06-10	1	-34/+34
*	soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driver	Furquan Shaikh	2021-01-25	1	-416/+141
*	soc/intel/tigerlake: Reflow long lines	Sridhar Siricilla	2020-10-19	1	-4/+2
*	soc/intel/tigerlake: add common routine for DDR init	Nick Vaccaro	2020-08-06	1	-0/+17
*	src: Remove extra lines in license header	Elyes HAOUAS	2020-07-26	1	-5/+1
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	soc/intel/tigerlake: Check SPD is not NULL before print	Eric Lai	2020-04-29	1	-1/+6
*	soc/intel/tigerlake: fix call to print_spd_info()	Nick Vaccaro	2020-04-28	1	-2/+2
*	soc/intel/tigerlake: Fix FSP SPD index for DDR4	Furquan Shaikh	2020-04-25	1	-1/+9
*	soc/intel/tigerlake: Disable MrcSafeConfig	Srinidhi N Kaushik	2020-04-11	1	-1/+0
*	soc/intel/tigerlake: Add support to initialize DDR4 Memory	Varun Joshi	2020-04-10	1	-0/+132
*	soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD.	Srinidhi N Kaushik	2020-04-05	1	-1/+9
*	soc/intel/tigerlake: Reorganize memory initialization support	Furquan Shaikh	2020-04-02	1	-107/+234
*	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra	2020-04-01	1	-0/+163