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path: root/src/soc/intel/tigerlake/meminit.c
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* soc/intel/tigerlake/meminit.c: Fix clang static assertsArthur Heymans2022-05-131-2/+4
* {mb, soc}: Move mrc_cache invalidating logic into `memory` common codeSubrata Banik2022-03-151-2/+1
* soc/intel/common: Pass `FSPM_UPD *` argument for spd functionsSubrata Banik2022-03-151-2/+2
* {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik2022-03-151-1/+2
* mb, soc: Add the SPD_CACHE_ENABLEZhuohao Lee2022-03-021-1/+3
* soc/intel/tigerlake: Hook up FSP repositoryFelix Singer2021-06-101-34/+34
* soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driverFurquan Shaikh2021-01-251-416/+141
* soc/intel/tigerlake: Reflow long linesSridhar Siricilla2020-10-191-4/+2
* soc/intel/tigerlake: add common routine for DDR initNick Vaccaro2020-08-061-0/+17
* src: Remove extra lines in license headerElyes HAOUAS2020-07-261-5/+1
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/tigerlake: Check SPD is not NULL before printEric Lai2020-04-291-1/+6
* soc/intel/tigerlake: fix call to print_spd_info()Nick Vaccaro2020-04-281-2/+2
* soc/intel/tigerlake: Fix FSP SPD index for DDR4Furquan Shaikh2020-04-251-1/+9
* soc/intel/tigerlake: Disable MrcSafeConfigSrinidhi N Kaushik2020-04-111-1/+0
* soc/intel/tigerlake: Add support to initialize DDR4 MemoryVarun Joshi2020-04-101-0/+132
* soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD.Srinidhi N Kaushik2020-04-051-1/+9
* soc/intel/tigerlake: Reorganize memory initialization supportFurquan Shaikh2020-04-021-107/+234
* soc/intel/tigerlake: Remove Jasper Lake SoC referencesAamir Bohra2020-04-011-0/+163
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