| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel: Drop `romstage_pch_init()` function | Angel Pons | 2021-03-01 | 1 | -1/+0 |
| * | src: Remove leading blank lines from SPDX header | Elyes HAOUAS | 2020-05-18 | 1 | -3/+0 |
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 1 | -1/+0 |
| * | src/: Replace GPL boilerplate with SPDX headers | Patrick Georgi | 2020-05-09 | 1 | -9/+1 |
| * | soc/intel/tigerlake: Remove Jasper Lake SoC references | Aamir Bohra | 2020-04-01 | 1 | -2/+1 |
| * | soc: Remove copyright notices | Patrick Georgi | 2020-03-18 | 1 | -1/+0 |
| * | soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig | Maulik V Vaghela | 2020-01-13 | 1 | -1/+2 |
| * | soc/intel/tigerlake/romstage: Do initial SoC commit till romstage | Subrata Banik | 2019-11-09 | 1 | -0/+20 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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