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path: root/src/soc/intel/tigerlake
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* soc/intel/tigerlake: Add CPU ID for TGL B0Jamie Ryu2020-06-061-0/+1
* lp4x: Add new memory parts and generate SPDsFurquan Shaikh2020-06-061-0/+4
* soc/intel/tigerlake: Generate LP4x SPD files using gen_spd.goFurquan Shaikh2020-06-066-0/+169
* soc/tigerlake: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS2020-06-031-6/+5
* soc/intel/tigerlake: update elog to include CSME reset causesderek.huang2020-06-031-0/+12
* soc/intel/common/{pch,sata}: Remove SATA common code driverSubrata Banik2020-06-021-1/+0
* src: Remove unused 'include <bootstate.h>'Elyes HAOUAS2020-06-021-1/+0
* {icelake,jasperlake,skylake,tigerlake}/bootblock.c: Clean up includesElyes HAOUAS2020-06-021-3/+0
* src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS2020-06-021-1/+0
* soc/intel/tigerlake/acpi: Update pch_hda.asl to ASL2.0 syntaxVenkata Krishna Nimmagadda2020-05-311-8/+6
* soc/intel/tigerlake/acpi: Update camera_clock_ctl.asl to ASL2.0Venkata Krishna Nimmagadda2020-05-311-2/+1
* soc/intel/tigerlake: Configure TcssDma0En and TcssDma1EnJohn Zhao2020-05-302-6/+11
* soc/intel/tigerlake: Implement soc_get_pmc_mux_device()Tim Wawrzynczak2020-05-281-0/+20
* soc/intel/tigerlake: Generate PMC ACPI device at runtimeTim Wawrzynczak2020-05-283-29/+30
* soc/intel/tigerlake: Configure THCWonkyu Kim2020-05-281-0/+18
* soc/intel/tigerlake: Correct GPIO community PID configurationEric Lai2020-05-281-5/+5
* soc/intel/common: Improve Type16 SMBIOS tablesPatrick Rudolph2020-05-281-0/+14
* soc/intel/gma: Implement fsp_soc_get_igd_bar() in common codeNico Huber2020-05-272-17/+0
* soc/intel/gma: Move display and opregion init to common codeNico Huber2020-05-271-30/+0
* drivers/intel/gma: Move IGD OpRegion to CBMEMNico Huber2020-05-271-17/+2
* soc/intel/tigerlake: Remove MIPI clock setting from devicetreeSrinidhi N Kaushik2020-05-262-23/+0
* soc/intel/tigerlake: Delete unused configurationWonkyu Kim2020-05-261-6/+0
* soc/intel/tigerlake: Disable VMDWonkyu Kim2020-05-262-0/+11
* soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnableJohn Zhao2020-05-262-2/+11
* soc/intel/tigerlake: Fix wrong operation region for CPU to PCH methodJohn Zhao2020-05-261-2/+2
* soc/intel/{jsl,tgl}: Override PRERAM_CBMEM_CONSOLE_SIZE default valueSubrata Banik2020-05-231-0/+4
* soc/intel/tigerlake: Provide SoundWire controller propertiesDuncan Laurie2020-05-222-0/+72
* soc/intel/tigerlake: Add definition for PMC EPOCDuncan Laurie2020-05-222-0/+31
* tigerlake: enable DPTF functionality for volteerSumeet R Pawnikar2020-05-201-0/+3
* soc/intel/tigerlake: Add TCSS devices to soc_acpi_name()Duncan Laurie2020-05-201-34/+42
* soc/intel/tigerlake: Move pmc_soc_set_afterg3_en to pmutilTim Wawrzynczak2020-05-203-18/+17
* soc/intel/tigerlake: Move PMC PCI resources under PMC deviceTim Wawrzynczak2020-05-205-38/+34
* tigerlake: update processor power limits configurationSumeet R Pawnikar2020-05-204-5/+18
* soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfgBrandon Breitenstein2020-05-202-1/+14
* soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1EnJohn Zhao2020-05-183-5/+23
* soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect overrideEric Lai2020-05-182-0/+2
* soc/intel/tigerlake: Fix wrong operation region for CPU to PCH methodJohn Zhao2020-05-182-4/+4
* src: Remove leading blank lines from SPDX headerElyes HAOUAS2020-05-181-3/+0
* soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()Furquan Shaikh2020-05-141-3/+0
* soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4GFurquan Shaikh2020-05-141-1/+0
* soc/intel/tigerlake: Correct IRQ interruptWonkyu Kim2020-05-122-175/+121
* device/pci_device: Extract pci_domain_set_resources from SOCRaul E Rangel2020-05-121-5/+0
* soc/intel/tigerlake: Control SATA and DMI power optimizationShaunak Saha2020-05-122-0/+21
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-1179-79/+0
* soc/intel/tigerlake: Update C-State infoWonkyu Kim2020-05-113-62/+20
* src/: Replace GPL boilerplate with SPDX headersPatrick Georgi2020-05-091-9/+1
* soc/intel: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS2020-05-081-12/+1
* soc/intel/tigerlake: Add PMC to platform ACPI name entryJohn Zhao2020-05-071-0/+1
* treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi2020-05-067-84/+7
* treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi2020-05-068-16/+8
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