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* soc/intel/{baytrail,broadwell}: Add missing <cbmem.h>Angel Pons2021-02-082-0/+2
* soc/intel/braswell,skylake: Drop logo parameters from devicetreeKyösti Mälkki2021-02-084-15/+0
* soc/intel: Drop CID1 from GNVSKyösti Mälkki2021-02-0811-32/+4
* soc/intel/broadwell/include/soc/me.h: Clean includesElyes HAOUAS2021-02-071-1/+1
* soc/intel/quark/storage_test.c: Remove redundant <commonlib/cbmem_id.h>Elyes HAOUAS2021-02-071-1/+0
* acpi: Fix BERT size_t printf format errorBenjamin Doron2021-02-071-1/+1
* soc/intel/alderlake: Increase VBT size to 9 KiBMaulik V Vaghela2021-02-071-0/+4
* soc/intel/broadwell: Use common {DMI,EP,MCH}BAR accessorsAngel Pons2021-02-076-14/+17
* soc/intel/broadwell: Convert to ASL 2.0 syntaxElyes HAOUAS2021-02-071-7/+8
* drivers/intel/fsp2_0: Add support for MP services2 PPIAamir Bohra2021-02-065-5/+5
* intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPIFurquan Shaikh2021-02-066-6/+6
* intel: Drop FSP_PEIM_TO_PEIM_INTERFACEFurquan Shaikh2021-02-066-7/+6
* soc/intel/broadwell: Conditionally skip PRE_GRAPHICS_DELAYKyösti Mälkki2021-02-062-15/+0
* sb,soc/intel: Add wake source fields in GNVSKyösti Mälkki2021-02-063-1/+7
* soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki2021-02-051-5/+1
* soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speedTim Chu2021-02-051-0/+6
* soc/intel/skylake/acpi/irqlinks.asl: Fix typo in commentElyes HAOUAS2021-02-051-1/+1
* soc/intel/alderlake: Refactor PCIE port configEric Lai2021-02-053-59/+75
* soc/intel/broadwell/pch/lpc.c: Program GEN_PMCON_3 in one writeAngel Pons2021-02-051-13/+9
* drivers/intel/fsp2_0: Fix running on x86_64Patrick Rudolph2021-02-041-3/+3
* acpi: Add support for reporting CrashLog in BERT tableFrancois Toguo2021-02-041-0/+11
* soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0John Zhao2021-02-041-2/+0
* src: Remove unused <bootstate.h>Elyes HAOUAS2021-02-042-2/+1
* soc/intel/tgl: Add configurable value for ConfigTdpLevelDerek Huang2021-02-031-0/+3
* pci_ids/intel: Add missing CFL-S GT1 IGD IDsNico Huber2021-02-032-0/+4
* pci_ids/intel: Correct 0x3e96, it's a CFL-S partNico Huber2021-02-032-2/+2
* src: Remove unused <cbmem.h>Elyes HAOUAS2021-02-0314-14/+0
* intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is selectedJohnny Lin2021-02-031-0/+1
* soc/intel: Fix compilation on x86_64Patrick Rudolph2021-02-031-4/+4
* soc/intel/baytrail,braswell: Drop TOLM from GNVSKyösti Mälkki2021-02-028-12/+30
* soc/intel/baytrail,braswell: Sync PCI memory region in ASLKyösti Mälkki2021-02-022-4/+4
* soc/intel/broadwell/gma.c: Add missing `break` in switchAngel Pons2021-02-011-0/+1
* soc/intel/skylake/Kconfig: Remove duplicated INTEL_DESCRIPTOR_MODE_CAPABLEElyes HAOUAS2021-02-011-1/+0
* src/soc/intel: Remove CPU_INTEL_COMMON_SMM selectionElyes HAOUAS2021-02-013-4/+0
* src: Remove unused <cpu/x86/smm.h>Elyes HAOUAS2021-02-014-4/+0
* soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQSubrata Banik2021-02-012-5/+10
* soc/intel/elkhartlake: Config PlatformDebugConsentFrans Hendriks2021-02-011-0/+3
* soc/intel/common/sata: Add support for Cannon Lake SATA (HALO)Erik van den Bogaert2021-02-011-0/+1
* soc/intel/broadwell/pch/sata.c: Don't enable Bus MasterAngel Pons2021-02-011-3/+2
* soc/intel/*: Get rid of custom microcode cachingPatrick Rudolph2021-02-014-30/+6
* soc/intel/xeon_sp: Use native CAR teardownArthur Heymans2021-02-012-9/+16
* drivers/intel/fsp2_0: Use coreboot postcar with FSP-TArthur Heymans2021-02-011-0/+4
* soc/intel/*: drop incomplete and unneeded check for DMI SRLOCKMichael Niewöhner2021-01-317-111/+7
* soc/intel/broadwell/pch: Drop some `config_of` usesAngel Pons2021-01-302-14/+24
* soc/intel/broadwell: Move `ramstage.c` to PCH scopeAngel Pons2021-01-303-1/+1
* soc/intel/broadwell: Make `broadwell_init_pre_device` staticAngel Pons2021-01-303-8/+5
* soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig optionsAngel Pons2021-01-3012-32/+18
* soc/intel/broadwell: Define and use MMCONF_BUS_NUMBERAngel Pons2021-01-306-20/+26
* soc/intel/broadwell: Use common SMBus codeAngel Pons2021-01-303-50/+3
* soc/intel/{baytrail,broadwell} Fix building with refcode blobsAngel Pons2021-01-302-12/+12
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