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* soc/intel/common/block/irq: Add support for intel_write_pci0_PRTTim Wawrzynczak2021-06-293-0/+54
| | | | | | | | | | | | | Add a new function to fill out the data structures necessary to generate a _PRT table. BUG=b:130217151, b:171580862, b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51159 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Add new IRQ moduleTim Wawrzynczak2021-06-294-0/+402
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel FSP provides a default set of IO-APIC IRQs for PCI devices, if the DevIntConfigPtr UPD is not filled in. However, the FSP has a list of rules that the input IRQ table must conform to: 1) One entry per slot/function 2) Functions using PIRQs must use IOxAPIC IRQs 16-23 3) Single-function devices must use INTA 4) Each slot must have consistent INTx<->PIRQy mappings 5) Some functions have special interrupt pin requirements 6) PCI Express RPs must be assigned in a special way (FIXED_INT_PIN) 7) Some functions require a unique IRQ number 8) PCI functions must avoid sharing an IRQ with a GPIO pad which routes its IRQ through IO-APIC. Since the FSP has no visibility into the actual GPIOs used on the board when GpioOverride is selected, IRQ conflicts can occur between PCI devices and GPIOs. This patch gives SoC code the ability to generate a table of PCI IRQs that will meet the BWG/FSP rules and also not conflict with GPIO IRQs. BUG=b:130217151, b:171580862, b:176858827 TEST=Boot with patch series on volteer, verify IO-APIC IRQs in `/proc/interrupts` match what is expected. No `GSI INT` or `could not derive routing` messages seen in `dmesg` output. Verified TPM, touchpad, touchscreen IRQs all function as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0c22a08ce589fa80d0bb1e637422304a3af2045c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49408 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* southbridge/intel/common: Move invalid PIRQ value to 0Tim Wawrzynczak2021-06-291-8/+8
| | | | | | | | | | | This makes structs that contain an `enum pirq` field that is default-initialized have the value PIRQ_INVALID Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idb4c7d79de13de0e4b187a42e8bdb27e25e61cc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55281 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Drop casts around `soc_read_pmc_base()`Angel Pons2021-06-2810-25/+18
| | | | | | | | | | | | | | | | | The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then casted to a pointer type for use with `read32()` and/or `write32()`. But since commit b324df6a540d154cc9267c0398654f9142aae052 (arch/x86: Provide readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()` functions live in `arch/mmio.h`. These functions use the `uintptr_t type for the address parameter instead of a pointer type, and using them with the `soc_read_pmc_base()` function allows dropping the casts to pointer. Change-Id: Iaf16e6f23d139e6f79360d9a29576406b7b15b07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* xeon_sp/{cpx,skx}: Add config IFD_CHIPSET 'lbg'Johnny Lin2021-06-282-0/+8
| | | | | | | | | | This is needed for ifdtool -p to detect CPX and SKX Lewisburg PCH as IFDv2. Change-Id: I21df9f700aedf131a38a776e76722bf918e6af84 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55746 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/jasperlake: Select DISPLAY_FSP_VERSION_INFO_2Ronak Kanabar2021-06-261-1/+1
| | | | | | | | | | | | | | | | | | | | Select DISPLAY_FSP_VERSION_INFO_2 for Jasper Lake soc. BUG=b:153038236 BRANCH=None TEST=Verify JSLRVP build with all the patch in relation chain and verify the version output prints no junk data observed. couple of lines from logs are as below. Display FSP Version Info HOB Reference Code - CPU = 8.7.16.10 uCode Version = 0.0.0.1 Change-Id: If68b704c4304357b0046a510545fc213d7ed5887 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45907 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cache_as_ram.S: Fix CAR issues with BootguardArthur Heymans2021-06-261-0/+17
| | | | | | | | | | | | | | It looks like the 'clear_car' code does not properly fill the required cachelines so add code to fill cachelines explicitly. Change-Id: Id5d77295f6d24f9d2bc23f39f8772fd172ac8910 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christopher Meis <christopher.meis@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/apollolake: Drop `xdci_can_enable()` callAngel Pons2021-06-251-1/+1
| | | | | | | | | | | | The `xdci_can_enable()` function is called earlier to configure FSP-S UPDs. If it returned false, then the xDCI device will be disabled and the second `xdci_can_enable()` call will never be evaluated. Change-Id: I4bd08e3194ffccc79c8feaf8f34b2bb4077f760a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55789 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Fix the typo for FSP_S_CONFIG paramV Sowmya2021-06-251-1/+1
| | | | | | | | | | | | | | This patch fixes the typo introduced in commit b03cadf for renaming FSP_S_CONFIG param name to s_cfg. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I0a9b500e528c68033008f3f8955d6c9c9ba8a737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* soc/intel/apollolake/xdci.c: Use `dev` parameterAngel Pons2021-06-251-3/+2
| | | | | | | | | | The `dev` parameter already points to the xDCI device. Change-Id: I122cc642c86b30804dd1176f77f4e2e1ebea4aa0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55788 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/skylake: Use `devfn_disable()` to handle XDCIAngel Pons2021-06-251-9/+3
| | | | | | | | | | | Done for consistency with other Intel SoCs. This allows moving the pattern inside a helper function. Change-Id: If95c4b6c1602e56436150a931210692f14630694 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55787 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/skylake: Use `is_devfn_enabled()`Angel Pons2021-06-255-57/+24
| | | | | | | | | | Use the `is_devfn_enabled()` function for the sake of brevity. Change-Id: Ic848767799e165200f26c2d5a58fbd3b72b9c240 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55786 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/cse: Add support for sending CSE End-of-Post messageTim Wawrzynczak2021-06-254-0/+124
| | | | | | | | | | | | | | | | | | | | | | The CSE expects the boot firmware to send it an End-of-Post message before loading the OS. This is a security feature, and is done to ensure that the CSE will no longer perform certain sensitive commands that are not intended to be exposed to the OS. If processing the EOP message fails in any way on a ChromeOS build, (and not already in recovery mode), recovery mode will be triggered, otherwise the CSME BWG will be followed, which is in the following commit. BUG=b:191362590 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6f667905f759cc2337daca4cc6e09694e68ab7e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/intel/alderlake: Update s0ix cstate tableBernardo Perez Priego2021-06-251-1/+1
| | | | | | | | | | | | | | | | Cstate C7 is not supported in ADL, replacing this unsupported state with C6 in the s0ix cstate table. BUG=None TEST=Boot device to OS. Print supported CStates and latencies. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I471f71481d337e3fafa4acab7fe8a39677c8710c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55734 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cache_as_ram.S: Fix SOC_INTEL_APOLLOLAKEArthur Heymans2021-06-243-0/+11
| | | | | | | | | | | Intel Apollolake does not support the bootguard MSRs 0x139 MSR_BC_PBEC and 0x13A MSR_BOOT_GUARD_SACM_INFO. Change-Id: Ief40028a1c85084e012a83db8080d478e407487b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* soc/intel/cache_as_ram.S: Add macro to detect bootguard nemArthur Heymans2021-06-241-6/+14
| | | | | | | | | Change-Id: I3867fce29d23b647fad9845b9a5c08bb949fa354 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Update mainboard_memory_init_params() argumentSubrata Banik2021-06-242-3/+3
| | | | | | | | | | | | | | This patch updates mainboard_memory_init_params() function argument from FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params() function don't need to override anything other than FSP_M_CONFIG UPDs hence passing config block alone rather passing entire FSP-M UPD structure. Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Refactor soc_silicon_init_params functionSubrata Banik2021-06-241-33/+132
| | | | | | | | | | | | | | | | | This patch create separate helper functions to fill-in required FSP-S UPDs as per IP initialization categories. This would help to increase the code readability and in future meaningful addition of FSP-S UPDs is possible rather adding UPDs randomly. TEST=FSP-S UPD dump shows no change without and with this code change. Change-Id: Iba51aebc74456449e24e51e2f309f14f951464a0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55233 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Rename FSP_S_CONFIG variable from params to s_cfgSubrata Banik2021-06-241-87/+87
| | | | | | | | | | | | | | | Align FSP-S UPD structure (FSP_S_CONFIG) variable name (s_cfg) as FSP-M UPD structure variable (m_cfg). TEST=Able to build and boot ADLRVP to ChromeOS. FSP-S UPD dump shows no change in UPD values with this CL. Change-Id: I795f733f5f0cc64d3a556a1cd401323b35ba5a23 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Refactor platform_fsp_silicon_init_params_cb functionSubrata Banik2021-06-241-9/+20
| | | | | | | | | | | | | | | | | Align platform_fsp_silicon_init_params_cb() function implementation with romstage/fsp_params.c file platform_fsp_memory_init_params_cb() as: |- Override FSP-S Arch UPD(s) using arch_silicon_init_params(). |- Override FSP-S SoC UPDs using soc_silicon_init_params(). |- Override FSP-S Mainboard UPDs using mainboard_silicon_init_params(). TEST=FSP-S UPD dump shows no change without and with this code change. Change-Id: I4cf0b8423fb4038a7feddd97ff585027b3012605 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common: Fix X2APIC NMI entry in ACPI MADTKyösti Mälkki2021-06-231-1/+1
| | | | | | | | | | | | For X2APIC mode, replicate the APIC NMI entry flags and intention to address all the logical processors. Change-Id: I9c0537a3efba942329f80d7cfdbd910b8958516f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55182 Reviewed-by: Lance Zhao Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Use is_devfn_enabled() for Device4Enable UPDSubrata Banik2021-06-231-3/+2
| | | | | | | | | | | | | | 1. Replace pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled() while enabling Thermal config. 2. Remove unused local variable of device structure type (struct device *). Change-Id: Icc2a44d6d3f1a78bf47354049dd9e2a0ed2282ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/alderlake: Use devfn_disable() function for XDCISubrata Banik2021-06-231-9/+3
| | | | | | | | | | | | | | | | | | Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I5e10e5d0b80986e1e73573a86a957985840fe0b3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55727 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: Use devfn_disable() function for XDCISubrata Banik2021-06-231-7/+3
| | | | | | | | | | | | | | | | | | Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I64ab77bc49d93aca1da0126d849e69ff75b182a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55726 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Use devfn_disable() function for XDCISubrata Banik2021-06-231-9/+3
| | | | | | | | | | | | | | | | | | | Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I8ca0813e18da0f95eb9293b6d0bbdf933a1e7039 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55725 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/icelake: Use devfn_disable() function for XDCISubrata Banik2021-06-231-4/+2
| | | | | | | | | | | | | | | | | | Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I568cd39792eba1bbace4901e96d708d80f73c60a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55724 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/jasperlake: Use devfn_disable() function for XDCISubrata Banik2021-06-231-9/+3
| | | | | | | | | | | | | | | | | | | Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I038e43deead70d598cf26f320dd9993f17591b88 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55723 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tigerlake: Use devfn_disable() function for XDCISubrata Banik2021-06-231-8/+3
| | | | | | | | | | | | | | | | | | Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I0e400ded7ba268a5f289b0ac568598e0dad1899a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55722 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/icelake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-232-43/+15
| | | | | | | | | | | | | | | | | | | | 1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. 4. Leave SATA, eMMC controller FSP UPDs at default state if controller is not enabled and FSP UPDs are set to disable. TEST=Able to build and boot without any regression seen on ICLRVP. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Id6861af3b5d1ce4f44b6d2109301bd4f5857f324 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/common: Unbreak masterTim Wawrzynczak2021-06-221-1/+1
| | | | | | | | | | | | | | Commit 54b03569c moved a call to cse_trigger_recovery () around, and commit 09635f418 renamed the function, but was tested before the first commit was submitted, thus breaking the tree. Fix it. Change-Id: If21ea0c1ebf9ce85c59ee25ec7f879abde2e3259 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55766 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/cse: Move cse_trigger_recovery functionTim Wawrzynczak2021-06-223-27/+27
| | | | | | | | | | | | | This function could be applicable in situations other than just for the CSE Lite SKU, therefore move this from cse_lite.c to cse.c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibc541f2e30ef06856da10f1f1219930dff493afa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55673 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/{apl,cnl}: Remove FSP CAR optionArthur Heymans2021-06-225-126/+5
| | | | | | | | | | | | | | | | One of the reason FSP-T support had to be kept in place was for Intel Bootguard. This now works with native CAR code, so there is no reason to keep FSP-T as an option for these platforms. APL did not even build with FSP_CAR and finding FSP-T using walkcbfs was only recently fixed using FMAP, so there can be no doubt that this option was never used with coreboot master. Change-Id: I0d5844b5a6fd291a13e5f467f4fc682b17eafa63 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/car: Add support for bootguard CARArthur Heymans2021-06-221-0/+28
| | | | | | | | | | | | | | | | Bootguard sets up CAR/NEM on its own so the only thing needed is to find free MTRRs for our own CAR region and clear that area to fill in cache lines. TESTED on prodrive/hermes with bootguard enabled. Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* soc/intel/common/cache_as_ram.S: Add macro to clear CARArthur Heymans2021-06-221-20/+22
| | | | | | | | | | | | | Add a macro to clear CAR which is replicated 3 times in this code. TEST: with BUILD_TIMELESS=1 the resulting binary is identical. Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* soc/intel/common/cache_as_ram.S: Add macro to find a free MTRRArthur Heymans2021-06-221-6/+44
| | | | | | | | | | | | | | This adds a macro to find an available MTRR(s) to set up CAR. This added complexity is not required on bootpaths without bootguard but with bootguard MTRR's have already been set up by the ACM so we need to figure out at runtime which ones are available. Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* soc/intel/common: Check CSE Lite RW statusSridahr Siricilla2021-06-211-3/+3
| | | | | | | | | | | | | | | | | The patch moves CSE Lite RW status check out of CSE RW update logic as the RW sanity check has to be done irrespective of CSE RW update logic is enabled or not. If coreboot detects CSE Lite RW status is not good, the coreboot triggers recovery. TEST=Verified boot on Brya Signed-off-by: Sridahr Siricilla <sridhar.siricilla@intel.com> Change-Id: I582b6cf24f8894c80ab461ca21f7c6e8caa738bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55619 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake: Use devfn_disable() functionSubrata Banik2021-06-211-3/+2
| | | | | | | | | | | | | | | | | | Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:15.1: enabled 0`. Change-Id: I449beae59d2f578c027d8110c03fa79f516c3fe9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/common: Add InSMM.STS supportAngel Pons2021-06-212-3/+26
| | | | | | | | | | | | | | | Tested on HP 280 G2, SMMSTORE v1 and v2 still work. Other tests: - If one does not set BIOS_CONTROL bit WPD, SMMSTORE breaks. - If one does not write the magic MSR `or 1`, SMMSTORE breaks. Change-Id: Ia90c0e3f8ccf895bfb6d46ffe26750393dab95fb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* security/intel: Add option to enable SMM flash access onlyAngel Pons2021-06-214-27/+50
| | | | | | | | | | | | | | | | | | On platforms where the boot media can be updated externally, e.g. using a BMC, add the possibility to enable writes in SMM only. This allows to protect the BIOS region even without the use of vboot, but keeps SMMSTORE working for use in payloads. Note that this breaks flashconsole, since the flash becomes read-only. Tested on Asrock B85M Pro4 and HP 280 G2, SMM BIOS write protection works as expected, and SMMSTORE can still be used. Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* security/intel/cbnt: Add loggingArthur Heymans2021-06-211-0/+5
| | | | | | | | | | This decodes and logs the CBnT status and error registers. Change-Id: I8b57132bedbd944b9861ab0e2e0d14723cb61635 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54093 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Add GFx Device ID 0x46b3Meera Ravindranath2021-06-212-0/+2
| | | | | | | | | | | | | | | | | List of changes: 1. Add new GFx ID 0x46B3 into device/pci_ids.h 2. Update new GFx ID into common graphics.c 3. Add new GFx ID description into report_platform.c TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I4343c7343875eb40c2955f6f4dd98d6446852dc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
* soc/intel/elkhartlake: Expose In-Band ECC config to mainboardWerner Zeh2021-06-212-0/+36
| | | | | | | | | | | | | | | Elkhart Lake provides a feature called "In-Band ECC" which uses a piece of system DRAM to store the ECC information in. There are a few parameters in FSP-M to set this feature up as needed. This patch adds code to expose these parameters to the devicetree so that they can be configured on mainboard level as needed. Change-Id: I7a4953d7b35277de01daff04211450e3d1bd8103 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55668 Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/cse: Move enum csme_failure_reasonTim Wawrzynczak2021-06-212-43/+42
| | | | | | | | | | | | | | CSE error codes may be applicable to move than just CSE Lite SKU errors, therefore move this enum to the intelblocks/cse.h file so that it can be used in other CSE-related code. While copying, remove `LITE_SKU` from a few of the enum values that are not necessarily CSE Lite SKU-specific. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0351587c67ce12f781c536998ca18a6a804d080a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55672 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/smm: Add `mainboard_smi_finalize`Aseda Aboagye2021-06-191-0/+7
| | | | | | | | | | | | | | | | | This commit adds a method called `mainboard_smi_finalize` which provides a mechanism for a mainboard to execute some code as part of the finalize method in the SMM stage before SoC does its finalization. BUG=b:191189275 BRANCH=None TEST=Implement `mainboard_smi_finalize` on lalala and verify that the code executes in SMM. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: If1ee63431e3c2a5831a4656c3a361229acff3f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/intel/jasperlake: Add offsets for pad lockingAseda Aboagye2021-06-192-0/+2
| | | | | | | | | | | | | | | | | | This commit simply adds the offset for the PADCFGLOCK register for the Intel Jasper Lake platform. This enables pads to be locked. BUG=b:191189275 BRANCH=None TEST=Enable pad locking on lalala by calling `gpio_lock_pad` and verify that the pad configuration is locked and cannot be manipulated from the OS. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Iccfe536b4a881f081f22bcc258a375caad3ffcb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55648 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/gpio: Add `gpio_lock_pad()`Aseda Aboagye2021-06-192-0/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a method for locking a GPIO pad configuration and its TX state. When the configuration is locked, the following registers become Read-Only and software writes to these registers have no effect. Pad Configuration registers GPI_NMI_EN GPI_SMI_EN GPI_GPE_EN Note that this is only effective if the pad is owned by the host (set in the PAD_OWN register). Intel platforms that wish to leverage this function need to define the PADCFGLOCK offset for their platform. BUG=b:191189275 BRANCH=None TEST=With some other code, call gpio_lock_pad() against a pad and verify that the pad configuration is locked and the state of the pad cannot be changed from the OS. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Id3c0da2f6942099c0289ca1e33a33c176f49d380 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/intel/alderlake: Add TBT PCIe root ports enablementBernardo Perez Priego2021-06-181-0/+4
| | | | | | | | | | | | | Ports are enabled according to devicetree. BUG=none TEST=Boot device, TBT should be functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I57e8eb13484014c17d24ad564643f0d03d11bc58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common: Fix bugs for GPIO_LOCK_UNLOCKAseda Aboagye2021-06-182-7/+8
| | | | | | | | | | | | | | | | | | | | | Per the Intel External Design Specification (doc #618876), the opcode for GPIO_LOCK_UNLOCK is 0x13. This commit fixes a bug where the opcode was defined as 13 decimal instead of hexadecimal. Additionally, it fixes another issue where the `pcr_execute_sideband_msg()` function doesn't actually write the data when this opcode is selected. BUG=b:191189275 BRANCH=None TEST=With additional code that uses this opcode, verify that the lock functionality works by locking a pad in firmware and attempting to modify the configuration of the pad from the OS. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ie14fff595474cdfd647c2b36f1eeb5e018f67375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55556 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block: fix storage size of HEST log addressRocky Phagura2021-06-182-2/+2
| | | | | | | | | | | | | | This patch fixes the storage size to reflect the proper bits instead of bytes. It was a bug in the initial HEST patch (https://review.coreboot.org/c/coreboot/+/52090), and commit ID d4db36e672644ac7f528d12c5ce3539725456085 . Also fixed the comments to properly reflect the range being used. Change-Id: I9e968bb09f1c9cd805ff1d0849551b9c2ce2e2b6 Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55393 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/jasperlake: Make use of FSP_ARRAY_LOAD macroLean Sheng Tan2021-06-182-54/+12
| | | | | | | | | | | Add FSP_ARRAY_LOAD macro for checking and loading array type configs into array type UPDs to increase readability. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ia20cabcaf9724882c68633eb9b510230e993768c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-06 04:47:40 +0000